Searched refs:PA_FPGA (Results 1 – 4 of 4) sorted by relevance
37 #define PA_FPGA (PA_PERIPHERAL + 0x01000000) macro42 #define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */43 #define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */44 #define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */45 #define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */46 #define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */47 #define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */48 #define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */49 #define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */50 #define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */[all …]
50 #define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */ macro53 #define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */54 #define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */55 #define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */56 #define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */57 #define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */58 #define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */59 #define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */60 #define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */61 #define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */[all …]
54 #define PA_FPGA 0xB7000000 /* FPGA base address */ macro58 #define FPGA_ILSR1 (PA_FPGA + 0x02)59 #define FPGA_ILSR2 (PA_FPGA + 0x03)60 #define FPGA_ILSR3 (PA_FPGA + 0x04)61 #define FPGA_ILSR4 (PA_FPGA + 0x05)62 #define FPGA_ILSR5 (PA_FPGA + 0x06)63 #define FPGA_ILSR6 (PA_FPGA + 0x07)64 #define FPGA_ILSR7 (PA_FPGA + 0x08)65 #define FPGA_ILSR8 (PA_FPGA + 0x09)
55 #define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ macro