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Searched refs:PLL_CTL (Results 1 – 18 of 18) sorted by relevance

/arch/blackfin/mach-common/
Ddpmc_modes.S19 P0.H = hi(PLL_CTL);
20 P0.L = lo(PLL_CTL);
38 P0.H = hi(PLL_CTL);
39 P0.L = lo(PLL_CTL);
112 P0.H = hi(PLL_CTL);
113 P0.L = lo(PLL_CTL);
144 P0.H = hi(PLL_CTL);
145 P0.L = lo(PLL_CTL);
175 P0.H = hi(PLL_CTL);
176 P0.L = lo(PLL_CTL);
Dclocks-init.c101 bfin_write16(PLL_CTL, PLL_CTL_VAL); in init_clocks()
/arch/blackfin/include/mach-common/
Dpll.h75 _bfin_write_pll_relock(PLL_CTL, val); in bfin_write_PLL_CTL()
/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h17 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
DcdefBF532.h11 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h17 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
DcdefBF522.h11 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h15 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
DcdefBF512.h11 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h16 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
DcdefBF561.h15 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h14 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
DcdefBF534.h11 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h11 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
DcdefBF538.h12 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h17 #define PLL_CTL 0xffc00000 /* PLL Control Register */ macro
DcdefBF54x_base.h16 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
/arch/blackfin/kernel/
Ddebug-mmrs.c1331 D16(PLL_CTL); in bfin_debug_mmrs_init()