1 /* arch/arm/mach-s3c2410/include/mach/regs-timer.h 2 * 3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 4 * http://www.simtec.co.uk/products/SWLINUX/ 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * S3C2410 Timer configuration 11 */ 12 13 #ifndef __ASM_ARCH_REGS_TIMER_H 14 #define __ASM_ARCH_REGS_TIMER_H 15 16 #define S3C_TIMERREG(x) (S3C_VA_TIMER + (x)) 17 #define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c)) 18 19 #define S3C2410_TCFG0 S3C_TIMERREG(0x00) 20 #define S3C2410_TCFG1 S3C_TIMERREG(0x04) 21 #define S3C2410_TCON S3C_TIMERREG(0x08) 22 23 #define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44) 24 25 #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) 26 #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) 27 #define S3C2410_TCFG_PRESCALER1_SHIFT (8) 28 #define S3C2410_TCFG_DEADZONE_MASK (255<<16) 29 #define S3C2410_TCFG_DEADZONE_SHIFT (16) 30 31 #define S3C2410_TCFG1_MUX4_DIV2 (0<<16) 32 #define S3C2410_TCFG1_MUX4_DIV4 (1<<16) 33 #define S3C2410_TCFG1_MUX4_DIV8 (2<<16) 34 #define S3C2410_TCFG1_MUX4_DIV16 (3<<16) 35 #define S3C2410_TCFG1_MUX4_TCLK1 (4<<16) 36 #define S3C2410_TCFG1_MUX4_MASK (15<<16) 37 #define S3C2410_TCFG1_MUX4_SHIFT (16) 38 39 #define S3C2410_TCFG1_MUX3_DIV2 (0<<12) 40 #define S3C2410_TCFG1_MUX3_DIV4 (1<<12) 41 #define S3C2410_TCFG1_MUX3_DIV8 (2<<12) 42 #define S3C2410_TCFG1_MUX3_DIV16 (3<<12) 43 #define S3C2410_TCFG1_MUX3_TCLK1 (4<<12) 44 #define S3C2410_TCFG1_MUX3_MASK (15<<12) 45 46 47 #define S3C2410_TCFG1_MUX2_DIV2 (0<<8) 48 #define S3C2410_TCFG1_MUX2_DIV4 (1<<8) 49 #define S3C2410_TCFG1_MUX2_DIV8 (2<<8) 50 #define S3C2410_TCFG1_MUX2_DIV16 (3<<8) 51 #define S3C2410_TCFG1_MUX2_TCLK1 (4<<8) 52 #define S3C2410_TCFG1_MUX2_MASK (15<<8) 53 54 55 #define S3C2410_TCFG1_MUX1_DIV2 (0<<4) 56 #define S3C2410_TCFG1_MUX1_DIV4 (1<<4) 57 #define S3C2410_TCFG1_MUX1_DIV8 (2<<4) 58 #define S3C2410_TCFG1_MUX1_DIV16 (3<<4) 59 #define S3C2410_TCFG1_MUX1_TCLK0 (4<<4) 60 #define S3C2410_TCFG1_MUX1_MASK (15<<4) 61 62 #define S3C2410_TCFG1_MUX0_DIV2 (0<<0) 63 #define S3C2410_TCFG1_MUX0_DIV4 (1<<0) 64 #define S3C2410_TCFG1_MUX0_DIV8 (2<<0) 65 #define S3C2410_TCFG1_MUX0_DIV16 (3<<0) 66 #define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) 67 #define S3C2410_TCFG1_MUX0_MASK (15<<0) 68 69 #define S3C2410_TCFG1_MUX_DIV2 (0<<0) 70 #define S3C2410_TCFG1_MUX_DIV4 (1<<0) 71 #define S3C2410_TCFG1_MUX_DIV8 (2<<0) 72 #define S3C2410_TCFG1_MUX_DIV16 (3<<0) 73 #define S3C2410_TCFG1_MUX_TCLK (4<<0) 74 #define S3C2410_TCFG1_MUX_MASK (15<<0) 75 76 #define S3C64XX_TCFG1_MUX_DIV1 (0<<0) 77 #define S3C64XX_TCFG1_MUX_DIV2 (1<<0) 78 #define S3C64XX_TCFG1_MUX_DIV4 (2<<0) 79 #define S3C64XX_TCFG1_MUX_DIV8 (3<<0) 80 #define S3C64XX_TCFG1_MUX_DIV16 (4<<0) 81 #define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */ 82 #define S3C64XX_TCFG1_MUX_MASK (15<<0) 83 84 #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) 85 86 /* for each timer, we have an count buffer, an compare buffer and 87 * an observation buffer 88 */ 89 90 /* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */ 91 92 #define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00) 93 #define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04) 94 #define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08)) 95 96 #define S3C2410_TCON_T4RELOAD (1<<22) 97 #define S3C2410_TCON_T4MANUALUPD (1<<21) 98 #define S3C2410_TCON_T4START (1<<20) 99 100 #define S3C2410_TCON_T3RELOAD (1<<19) 101 #define S3C2410_TCON_T3INVERT (1<<18) 102 #define S3C2410_TCON_T3MANUALUPD (1<<17) 103 #define S3C2410_TCON_T3START (1<<16) 104 105 #define S3C2410_TCON_T2RELOAD (1<<15) 106 #define S3C2410_TCON_T2INVERT (1<<14) 107 #define S3C2410_TCON_T2MANUALUPD (1<<13) 108 #define S3C2410_TCON_T2START (1<<12) 109 110 #define S3C2410_TCON_T1RELOAD (1<<11) 111 #define S3C2410_TCON_T1INVERT (1<<10) 112 #define S3C2410_TCON_T1MANUALUPD (1<<9) 113 #define S3C2410_TCON_T1START (1<<8) 114 115 #define S3C2410_TCON_T0DEADZONE (1<<4) 116 #define S3C2410_TCON_T0RELOAD (1<<3) 117 #define S3C2410_TCON_T0INVERT (1<<2) 118 #define S3C2410_TCON_T0MANUALUPD (1<<1) 119 #define S3C2410_TCON_T0START (1<<0) 120 121 #endif /* __ASM_ARCH_REGS_TIMER_H */ 122 123 124 125