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Searched refs:S5P_CMU_CLKSTOP_G3D_LOWPWR (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
Dpmu.c45 { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
133 { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
/arch/arm/mach-exynos/include/mach/
Dregs-pmu.h82 #define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) macro