Searched refs:SPI0_CLK (Results 1 – 3 of 3) sorted by relevance
531 MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false)
1283 #define SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */ macro
127 #define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK)128 #define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val)