Searched refs:TIMER_ENABLE (Results 1 – 16 of 16) sorted by relevance
/arch/arm/mach-msm/ |
D | timer.c | 35 #define TIMER_ENABLE 0x0008 macro 55 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_interrupt() 57 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_interrupt() 66 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_set_next_event() 69 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_set_next_event() 78 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); in msm_timer_set_next_event() 87 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_set_mode() 101 writel_relaxed(ctrl, event_base + TIMER_ENABLE); in msm_timer_set_mode() 214 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); in msm_timer_init()
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/arch/hexagon/include/asm/ |
D | timer-regs.h | 26 #define TIMER_ENABLE 0 macro
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/arch/blackfin/include/asm/ |
D | gptimers.h | 22 # define TIMER0_GROUP_REG TIMER_ENABLE 59 # define TIMER0_GROUP_REG TIMER_ENABLE
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/arch/hexagon/kernel/ |
D | time.c | 96 iowrite32(1 << TIMER_ENABLE, &rtos_timer->enable); in set_next_event()
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/arch/blackfin/mach-bf533/include/mach/ |
D | defBF532.h | 97 #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ macro
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D | cdefBF532.h | 554 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) 555 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
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/arch/blackfin/mach-bf527/include/mach/ |
D | defBF522.h | 131 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ macro
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D | cdefBF522.h | 215 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) 216 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
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/arch/blackfin/mach-bf518/include/mach/ |
D | defBF512.h | 136 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ macro
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D | cdefBF512.h | 198 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) 199 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
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/arch/blackfin/mach-bf537/include/mach/ |
D | defBF534.h | 112 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ macro
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D | cdefBF534.h | 182 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) 183 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE,val)
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/arch/blackfin/mach-bf538/include/mach/ |
D | defBF538.h | 100 #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ macro
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D | cdefBF538.h | 210 #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) 211 #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
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/arch/blackfin/kernel/ |
D | bfin_gpio.c | 39 AWA_inen = TIMER_ENABLE,
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D | debug-mmrs.c | 1061 #ifdef TIMER_ENABLE in bfin_debug_mmrs_init() 1062 GPTIMER_GROUP(TIMER_ENABLE, -1); in bfin_debug_mmrs_init()
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