Searched refs:TWI0_CLKDIV (Results 1 – 8 of 8) sorted by relevance
376 #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ macro393 #define TWI0_REGBASE TWI0_CLKDIV
1376 .start = TWI0_CLKDIV,1377 .end = TWI0_CLKDIV + 0xFF,
456 #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ macro
430 #define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ macro
1545 #if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV) in bfin_debug_mmrs_init()1550 # ifdef TWI0_CLKDIV in bfin_debug_mmrs_init()
107 #define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ macro
596 #define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */ macro