1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqdomain.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/clcd.h>
31 #include <linux/amba/pl061.h>
32 #include <linux/amba/mmci.h>
33 #include <linux/amba/pl022.h>
34 #include <linux/io.h>
35 #include <linux/irqchip/arm-vic.h>
36 #include <linux/irqchip/versatile-fpga.h>
37 #include <linux/gfp.h>
38 #include <linux/clkdev.h>
39 #include <linux/mtd/physmap.h>
40 #include <linux/bitops.h>
41
42 #include <asm/irq.h>
43 #include <asm/hardware/arm_timer.h>
44 #include <asm/hardware/icst.h>
45 #include <asm/mach-types.h>
46
47 #include <asm/mach/arch.h>
48 #include <asm/mach/irq.h>
49 #include <asm/mach/time.h>
50 #include <asm/mach/map.h>
51 #include <mach/hardware.h>
52 #include <mach/platform.h>
53 #include <asm/hardware/timer-sp.h>
54
55 #include <plat/clcd.h>
56 #include <plat/sched_clock.h>
57
58 #include "core.h"
59
60 /*
61 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
62 * is the (PA >> 12).
63 *
64 * Setup a VA for the Versatile Vectored Interrupt Controller.
65 */
66 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
67 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
68
69 /* These PIC IRQs are valid in each configuration */
70 #define PIC_VALID_ALL BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \
71 BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \
72 BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \
73 BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \
74 BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \
75 BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \
76 BIT(SIC_INT_PCI3)
77 #if 1
78 #define IRQ_MMCI0A IRQ_VICSOURCE22
79 #define IRQ_AACI IRQ_VICSOURCE24
80 #define IRQ_ETH IRQ_VICSOURCE25
81 #define PIC_MASK 0xFFD00000
82 #define PIC_VALID PIC_VALID_ALL
83 #else
84 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
85 #define IRQ_AACI IRQ_SIC_AACI
86 #define IRQ_ETH IRQ_SIC_ETH
87 #define PIC_MASK 0
88 #define PIC_VALID PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \
89 BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \
90 BIT(SIC_INT_ETH)
91 #endif
92
93 /* Lookup table for finding a DT node that represents the vic instance */
94 static const struct of_device_id vic_of_match[] __initconst = {
95 { .compatible = "arm,versatile-vic", },
96 {}
97 };
98
99 static const struct of_device_id sic_of_match[] __initconst = {
100 { .compatible = "arm,versatile-sic", },
101 {}
102 };
103
versatile_init_irq(void)104 void __init versatile_init_irq(void)
105 {
106 struct device_node *np;
107
108 np = of_find_matching_node_by_address(NULL, vic_of_match,
109 VERSATILE_VIC_BASE);
110 __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
111
112 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
113
114 np = of_find_matching_node_by_address(NULL, sic_of_match,
115 VERSATILE_SIC_BASE);
116
117 fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
118 IRQ_VICSOURCE31, PIC_VALID, np);
119
120 /*
121 * Interrupts on secondary controller from 0 to 8 are routed to
122 * source 31 on PIC.
123 * Interrupts from 21 to 31 are routed directly to the VIC on
124 * the corresponding number on primary controller. This is controlled
125 * by setting PIC_ENABLEx.
126 */
127 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
128 }
129
130 static struct map_desc versatile_io_desc[] __initdata __maybe_unused = {
131 {
132 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
133 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
134 .length = SZ_4K,
135 .type = MT_DEVICE
136 }, {
137 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
138 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
139 .length = SZ_4K,
140 .type = MT_DEVICE
141 }, {
142 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
143 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
144 .length = SZ_4K,
145 .type = MT_DEVICE
146 }, {
147 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
148 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
149 .length = SZ_4K * 9,
150 .type = MT_DEVICE
151 },
152 #ifdef CONFIG_MACH_VERSATILE_AB
153 {
154 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
155 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
156 .length = SZ_64M,
157 .type = MT_DEVICE
158 },
159 #endif
160 #ifdef CONFIG_DEBUG_LL
161 {
162 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
163 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
164 .length = SZ_4K,
165 .type = MT_DEVICE
166 },
167 #endif
168 #ifdef CONFIG_PCI
169 {
170 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
171 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
172 .length = SZ_4K,
173 .type = MT_DEVICE
174 }, {
175 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
176 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
177 .length = VERSATILE_PCI_BASE_SIZE,
178 .type = MT_DEVICE
179 }, {
180 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
181 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
182 .length = VERSATILE_PCI_CFG_BASE_SIZE,
183 .type = MT_DEVICE
184 },
185 #endif
186 };
187
versatile_map_io(void)188 void __init versatile_map_io(void)
189 {
190 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
191 }
192
193
194 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
195
versatile_flash_set_vpp(struct platform_device * pdev,int on)196 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
197 {
198 u32 val;
199
200 val = __raw_readl(VERSATILE_FLASHCTRL);
201 if (on)
202 val |= VERSATILE_FLASHPROG_FLVPPEN;
203 else
204 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
205 __raw_writel(val, VERSATILE_FLASHCTRL);
206 }
207
208 static struct physmap_flash_data versatile_flash_data = {
209 .width = 4,
210 .set_vpp = versatile_flash_set_vpp,
211 };
212
213 static struct resource versatile_flash_resource = {
214 .start = VERSATILE_FLASH_BASE,
215 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
216 .flags = IORESOURCE_MEM,
217 };
218
219 static struct platform_device versatile_flash_device = {
220 .name = "physmap-flash",
221 .id = 0,
222 .dev = {
223 .platform_data = &versatile_flash_data,
224 },
225 .num_resources = 1,
226 .resource = &versatile_flash_resource,
227 };
228
229 static struct resource smc91x_resources[] = {
230 [0] = {
231 .start = VERSATILE_ETH_BASE,
232 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
233 .flags = IORESOURCE_MEM,
234 },
235 [1] = {
236 .start = IRQ_ETH,
237 .end = IRQ_ETH,
238 .flags = IORESOURCE_IRQ,
239 },
240 };
241
242 static struct platform_device smc91x_device = {
243 .name = "smc91x",
244 .id = 0,
245 .num_resources = ARRAY_SIZE(smc91x_resources),
246 .resource = smc91x_resources,
247 };
248
249 static struct resource versatile_i2c_resource = {
250 .start = VERSATILE_I2C_BASE,
251 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
252 .flags = IORESOURCE_MEM,
253 };
254
255 static struct platform_device versatile_i2c_device = {
256 .name = "versatile-i2c",
257 .id = 0,
258 .num_resources = 1,
259 .resource = &versatile_i2c_resource,
260 };
261
262 static struct i2c_board_info versatile_i2c_board_info[] = {
263 {
264 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
265 },
266 };
267
versatile_i2c_init(void)268 static int __init versatile_i2c_init(void)
269 {
270 return i2c_register_board_info(0, versatile_i2c_board_info,
271 ARRAY_SIZE(versatile_i2c_board_info));
272 }
273 arch_initcall(versatile_i2c_init);
274
275 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
276
mmc_status(struct device * dev)277 unsigned int mmc_status(struct device *dev)
278 {
279 struct amba_device *adev = container_of(dev, struct amba_device, dev);
280 u32 mask;
281
282 if (adev->res.start == VERSATILE_MMCI0_BASE)
283 mask = 1;
284 else
285 mask = 2;
286
287 return readl(VERSATILE_SYSMCI) & mask;
288 }
289
290 static struct mmci_platform_data mmc0_plat_data = {
291 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
292 .status = mmc_status,
293 .gpio_wp = -1,
294 .gpio_cd = -1,
295 };
296
297 static struct resource char_lcd_resources[] = {
298 {
299 .start = VERSATILE_CHAR_LCD_BASE,
300 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
301 .flags = IORESOURCE_MEM,
302 },
303 };
304
305 static struct platform_device char_lcd_device = {
306 .name = "arm-charlcd",
307 .id = -1,
308 .num_resources = ARRAY_SIZE(char_lcd_resources),
309 .resource = char_lcd_resources,
310 };
311
312 /*
313 * Clock handling
314 */
315 static const struct icst_params versatile_oscvco_params = {
316 .ref = 24000000,
317 .vco_max = ICST307_VCO_MAX,
318 .vco_min = ICST307_VCO_MIN,
319 .vd_min = 4 + 8,
320 .vd_max = 511 + 8,
321 .rd_min = 1 + 2,
322 .rd_max = 127 + 2,
323 .s2div = icst307_s2div,
324 .idx2s = icst307_idx2s,
325 };
326
versatile_oscvco_set(struct clk * clk,struct icst_vco vco)327 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
328 {
329 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
330 u32 val;
331
332 val = readl(clk->vcoreg) & ~0x7ffff;
333 val |= vco.v | (vco.r << 9) | (vco.s << 16);
334
335 writel(0xa05f, sys_lock);
336 writel(val, clk->vcoreg);
337 writel(0, sys_lock);
338 }
339
340 static const struct clk_ops osc4_clk_ops = {
341 .round = icst_clk_round,
342 .set = icst_clk_set,
343 .setvco = versatile_oscvco_set,
344 };
345
346 static struct clk osc4_clk = {
347 .ops = &osc4_clk_ops,
348 .params = &versatile_oscvco_params,
349 };
350
351 /*
352 * These are fixed clocks.
353 */
354 static struct clk ref24_clk = {
355 .rate = 24000000,
356 };
357
358 static struct clk sp804_clk = {
359 .rate = 1000000,
360 };
361
362 static struct clk dummy_apb_pclk;
363
364 static struct clk_lookup lookups[] = {
365 { /* AMBA bus clock */
366 .con_id = "apb_pclk",
367 .clk = &dummy_apb_pclk,
368 }, { /* UART0 */
369 .dev_id = "dev:f1",
370 .clk = &ref24_clk,
371 }, { /* UART1 */
372 .dev_id = "dev:f2",
373 .clk = &ref24_clk,
374 }, { /* UART2 */
375 .dev_id = "dev:f3",
376 .clk = &ref24_clk,
377 }, { /* UART3 */
378 .dev_id = "fpga:09",
379 .clk = &ref24_clk,
380 }, { /* KMI0 */
381 .dev_id = "fpga:06",
382 .clk = &ref24_clk,
383 }, { /* KMI1 */
384 .dev_id = "fpga:07",
385 .clk = &ref24_clk,
386 }, { /* MMC0 */
387 .dev_id = "fpga:05",
388 .clk = &ref24_clk,
389 }, { /* MMC1 */
390 .dev_id = "fpga:0b",
391 .clk = &ref24_clk,
392 }, { /* SSP */
393 .dev_id = "dev:f4",
394 .clk = &ref24_clk,
395 }, { /* CLCD */
396 .dev_id = "dev:20",
397 .clk = &osc4_clk,
398 }, { /* SP804 timers */
399 .dev_id = "sp804",
400 .clk = &sp804_clk,
401 },
402 };
403
404 /*
405 * CLCD support.
406 */
407 #define SYS_CLCD_MODE_MASK (3 << 0)
408 #define SYS_CLCD_MODE_888 (0 << 0)
409 #define SYS_CLCD_MODE_5551 (1 << 0)
410 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
411 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
412 #define SYS_CLCD_NLCDIOON (1 << 2)
413 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
414 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
415 #define SYS_CLCD_ID_MASK (0x1f << 8)
416 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
417 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
418 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
419 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
420 #define SYS_CLCD_ID_VGA (0x1f << 8)
421
422 static bool is_sanyo_2_5_lcd;
423
424 /*
425 * Disable all display connectors on the interface module.
426 */
versatile_clcd_disable(struct clcd_fb * fb)427 static void versatile_clcd_disable(struct clcd_fb *fb)
428 {
429 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
430 u32 val;
431
432 val = readl(sys_clcd);
433 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
434 writel(val, sys_clcd);
435
436 #ifdef CONFIG_MACH_VERSATILE_AB
437 /*
438 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
439 */
440 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
441 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
442 unsigned long ctrl;
443
444 ctrl = readl(versatile_ib2_ctrl);
445 ctrl &= ~0x01;
446 writel(ctrl, versatile_ib2_ctrl);
447 }
448 #endif
449 }
450
451 /*
452 * Enable the relevant connector on the interface module.
453 */
versatile_clcd_enable(struct clcd_fb * fb)454 static void versatile_clcd_enable(struct clcd_fb *fb)
455 {
456 struct fb_var_screeninfo *var = &fb->fb.var;
457 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
458 u32 val;
459
460 val = readl(sys_clcd);
461 val &= ~SYS_CLCD_MODE_MASK;
462
463 switch (var->green.length) {
464 case 5:
465 val |= SYS_CLCD_MODE_5551;
466 break;
467 case 6:
468 if (var->red.offset == 0)
469 val |= SYS_CLCD_MODE_565_RLSB;
470 else
471 val |= SYS_CLCD_MODE_565_BLSB;
472 break;
473 case 8:
474 val |= SYS_CLCD_MODE_888;
475 break;
476 }
477
478 /*
479 * Set the MUX
480 */
481 writel(val, sys_clcd);
482
483 /*
484 * And now enable the PSUs
485 */
486 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
487 writel(val, sys_clcd);
488
489 #ifdef CONFIG_MACH_VERSATILE_AB
490 /*
491 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
492 */
493 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
494 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
495 unsigned long ctrl;
496
497 ctrl = readl(versatile_ib2_ctrl);
498 ctrl |= 0x01;
499 writel(ctrl, versatile_ib2_ctrl);
500 }
501 #endif
502 }
503
504 /*
505 * Detect which LCD panel is connected, and return the appropriate
506 * clcd_panel structure. Note: we do not have any information on
507 * the required timings for the 8.4in panel, so we presently assume
508 * VGA timings.
509 */
versatile_clcd_setup(struct clcd_fb * fb)510 static int versatile_clcd_setup(struct clcd_fb *fb)
511 {
512 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
513 const char *panel_name;
514 u32 val;
515
516 is_sanyo_2_5_lcd = false;
517
518 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
519 if (val == SYS_CLCD_ID_SANYO_3_8)
520 panel_name = "Sanyo TM38QV67A02A";
521 else if (val == SYS_CLCD_ID_SANYO_2_5) {
522 panel_name = "Sanyo QVGA Portrait";
523 is_sanyo_2_5_lcd = true;
524 } else if (val == SYS_CLCD_ID_EPSON_2_2)
525 panel_name = "Epson L2F50113T00";
526 else if (val == SYS_CLCD_ID_VGA)
527 panel_name = "VGA";
528 else {
529 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
530 val);
531 panel_name = "VGA";
532 }
533
534 fb->panel = versatile_clcd_get_panel(panel_name);
535 if (!fb->panel)
536 return -EINVAL;
537
538 return versatile_clcd_setup_dma(fb, SZ_1M);
539 }
540
versatile_clcd_decode(struct clcd_fb * fb,struct clcd_regs * regs)541 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
542 {
543 clcdfb_decode(fb, regs);
544
545 /* Always clear BGR for RGB565: we do the routing externally */
546 if (fb->fb.var.green.length == 6)
547 regs->cntl &= ~CNTL_BGR;
548 }
549
550 static struct clcd_board clcd_plat_data = {
551 .name = "Versatile",
552 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
553 .check = clcdfb_check,
554 .decode = versatile_clcd_decode,
555 .disable = versatile_clcd_disable,
556 .enable = versatile_clcd_enable,
557 .setup = versatile_clcd_setup,
558 .mmap = versatile_clcd_mmap_dma,
559 .remove = versatile_clcd_remove_dma,
560 };
561
562 static struct pl061_platform_data gpio0_plat_data = {
563 .gpio_base = 0,
564 .irq_base = IRQ_GPIO0_START,
565 };
566
567 static struct pl061_platform_data gpio1_plat_data = {
568 .gpio_base = 8,
569 .irq_base = IRQ_GPIO1_START,
570 };
571
572 static struct pl022_ssp_controller ssp0_plat_data = {
573 .bus_id = 0,
574 .enable_dma = 0,
575 .num_chipselect = 1,
576 };
577
578 #define AACI_IRQ { IRQ_AACI }
579 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
580 #define KMI0_IRQ { IRQ_SIC_KMI0 }
581 #define KMI1_IRQ { IRQ_SIC_KMI1 }
582
583 /*
584 * These devices are connected directly to the multi-layer AHB switch
585 */
586 #define SMC_IRQ { }
587 #define MPMC_IRQ { }
588 #define CLCD_IRQ { IRQ_CLCDINT }
589 #define DMAC_IRQ { IRQ_DMAINT }
590
591 /*
592 * These devices are connected via the core APB bridge
593 */
594 #define SCTL_IRQ { }
595 #define WATCHDOG_IRQ { IRQ_WDOGINT }
596 #define GPIO0_IRQ { IRQ_GPIOINT0 }
597 #define GPIO1_IRQ { IRQ_GPIOINT1 }
598 #define RTC_IRQ { IRQ_RTCINT }
599
600 /*
601 * These devices are connected via the DMA APB bridge
602 */
603 #define SCI_IRQ { IRQ_SCIINT }
604 #define UART0_IRQ { IRQ_UARTINT0 }
605 #define UART1_IRQ { IRQ_UARTINT1 }
606 #define UART2_IRQ { IRQ_UARTINT2 }
607 #define SSP_IRQ { IRQ_SSPINT }
608
609 /* FPGA Primecells */
610 APB_DEVICE(aaci, "fpga:04", AACI, NULL);
611 APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
612 APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
613 APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
614
615 /* DevChip Primecells */
616 AHB_DEVICE(smc, "dev:00", SMC, NULL);
617 AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
618 AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
619 AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
620 APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
621 APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
622 APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
623 APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
624 APB_DEVICE(rtc, "dev:e8", RTC, NULL);
625 APB_DEVICE(sci0, "dev:f0", SCI, NULL);
626 APB_DEVICE(uart0, "dev:f1", UART0, NULL);
627 APB_DEVICE(uart1, "dev:f2", UART1, NULL);
628 APB_DEVICE(uart2, "dev:f3", UART2, NULL);
629 APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
630
631 static struct amba_device *amba_devs[] __initdata = {
632 &dmac_device,
633 &uart0_device,
634 &uart1_device,
635 &uart2_device,
636 &smc_device,
637 &mpmc_device,
638 &clcd_device,
639 &sctl_device,
640 &wdog_device,
641 &gpio0_device,
642 &gpio1_device,
643 &rtc_device,
644 &sci0_device,
645 &ssp0_device,
646 &aaci_device,
647 &mmc0_device,
648 &kmi0_device,
649 &kmi1_device,
650 };
651
652 #ifdef CONFIG_OF
653 /*
654 * Lookup table for attaching a specific name and platform_data pointer to
655 * devices as they get created by of_platform_populate(). Ideally this table
656 * would not exist, but the current clock implementation depends on some devices
657 * having a specific name.
658 */
659 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
660 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
661 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
662 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
663 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
664 /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
665 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
666
667 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
668 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
669 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
670 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
671 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
672
673 #if 0
674 /*
675 * These entries are unnecessary because no clocks referencing
676 * them. I've left them in for now as place holders in case
677 * any of them need to be added back, but they should be
678 * removed before actually committing this patch. --gcl
679 */
680 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
681 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
682 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
683 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
684 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
685
686 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
687 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
688 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
689 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
690 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
691 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
692 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
693 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
694 #endif
695 {}
696 };
697 #endif
698
699 #ifdef CONFIG_LEDS
700 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
701
versatile_leds_event(led_event_t ledevt)702 static void versatile_leds_event(led_event_t ledevt)
703 {
704 unsigned long flags;
705 u32 val;
706
707 local_irq_save(flags);
708 val = readl(VA_LEDS_BASE);
709
710 switch (ledevt) {
711 case led_idle_start:
712 val = val & ~VERSATILE_SYS_LED0;
713 break;
714
715 case led_idle_end:
716 val = val | VERSATILE_SYS_LED0;
717 break;
718
719 case led_timer:
720 val = val ^ VERSATILE_SYS_LED1;
721 break;
722
723 case led_halted:
724 val = 0;
725 break;
726
727 default:
728 break;
729 }
730
731 writel(val, VA_LEDS_BASE);
732 local_irq_restore(flags);
733 }
734 #endif /* CONFIG_LEDS */
735
versatile_restart(char mode,const char * cmd)736 void versatile_restart(char mode, const char *cmd)
737 {
738 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
739 u32 val;
740
741 val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
742 val |= 0x105;
743
744 __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
745 __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
746 __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
747 }
748
749 /* Early initializations */
versatile_init_early(void)750 void __init versatile_init_early(void)
751 {
752 u32 val;
753 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
754
755 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
756 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
757
758 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
759
760 /*
761 * set clock frequency:
762 * VERSATILE_REFCLK is 32KHz
763 * VERSATILE_TIMCLK is 1MHz
764 */
765 val = readl(__io_address(VERSATILE_SCTL_BASE));
766 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
767 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
768 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
769 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
770 __io_address(VERSATILE_SCTL_BASE));
771 }
772
versatile_init(void)773 void __init versatile_init(void)
774 {
775 int i;
776
777 platform_device_register(&versatile_flash_device);
778 platform_device_register(&versatile_i2c_device);
779 platform_device_register(&smc91x_device);
780 platform_device_register(&char_lcd_device);
781
782 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
783 struct amba_device *d = amba_devs[i];
784 amba_device_register(d, &iomem_resource);
785 }
786 }
787
788 /*
789 * Where is the timer (VA)?
790 */
791 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
792 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
793 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
794 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
795
796 /*
797 * Set up timer interrupt, and return the current time in seconds.
798 */
versatile_timer_init(void)799 void __init versatile_timer_init(void)
800 {
801
802 /*
803 * Initialise to a known state (all timers off)
804 */
805 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
806 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
807 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
808 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
809
810 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
811 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
812 }
813