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Searched refs:_flags (Results 1 – 19 of 19) sorted by relevance

/arch/ia64/include/uapi/asm/
Dsiginfo.h63 unsigned int _flags; /* see below */ member
77 #define si_flags _sifields._sigfault._flags
/arch/sh/kernel/cpu/sh2a/
Dclock-sh7264.c80 #define DIV4(_reg, _bit, _mask, _flags) \ argument
81 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
Dclock-sh7269.c108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/arch/sh/kernel/cpu/sh4a/
Dclock-sh7366.c120 #define DIV4(_reg, _bit, _mask, _flags) \ argument
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
140 #define MSTP(_parent, _reg, _bit, _flags) \ argument
141 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7757.c65 #define DIV4(_bit, _mask, _flags) \ argument
66 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
Dclock-shx3.c64 #define DIV4(_bit, _mask, _flags) \ argument
65 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
Dclock-sh7343.c117 #define DIV4(_reg, _bit, _mask, _flags) \ argument
118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
137 #define MSTP(_parent, _reg, _bit, _flags) \ argument
138 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7785.c69 #define DIV4(_bit, _mask, _flags) \ argument
70 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
Dclock-sh7786.c70 #define DIV4(_bit, _mask, _flags) \ argument
71 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
Dclock-sh7722.c120 #define DIV4(_reg, _bit, _mask, _flags) \ argument
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
Dclock-sh7734.c72 #define DIV4(_reg, _bit, _mask, _flags) \ argument
73 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
Dclock-sh7723.c123 #define DIV4(_reg, _bit, _mask, _flags) \ argument
124 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
Dclock-sh7724.c162 #define DIV4(_reg, _bit, _mask, _flags) \ argument
163 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/arch/arm/mach-omap2/
Dclock.h52 _clkops_name, _flags) \ argument
59 .flags = _flags, \
105 _parent_ptr, _flags, \ argument
Dclockdomain.c831 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; in clkdm_sleep_nolock()
885 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; in clkdm_wakeup_nolock()
940 clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED; in clkdm_allow_idle_nolock()
989 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; in clkdm_deny_idle_nolock()
1028 ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false; in clkdm_in_hwsup()
Dclockdomain.h132 u8 _flags; member
/arch/arm/mach-shmobile/
Dclock-sh73a0.c226 #define DIV4(_reg, _bit, _mask, _flags) \ argument
227 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
462 #define MSTP(_parent, _reg, _bit, _flags) \ argument
463 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7372.c320 #define DIV4(_reg, _bit, _mask, _flags) \ argument
321 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
412 #define MSTP(_parent, _reg, _bit, _flags) \ argument
413 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
/arch/sparc/kernel/
Dperf_event.c1097 static void sparc_pmu_del(struct perf_event *event, int _flags) in sparc_pmu_del() argument