| /arch/x86/lib/ |
| D | usercopy_32.c | 54 _ASM_EXTABLE(0b,3b) \
55 _ASM_EXTABLE(1b,2b) \
160 _ASM_EXTABLE(1b,100b) in __copy_user_intel()
161 _ASM_EXTABLE(2b,100b) in __copy_user_intel()
162 _ASM_EXTABLE(3b,100b) in __copy_user_intel()
163 _ASM_EXTABLE(4b,100b) in __copy_user_intel()
164 _ASM_EXTABLE(5b,100b) in __copy_user_intel()
165 _ASM_EXTABLE(6b,100b) in __copy_user_intel()
166 _ASM_EXTABLE(7b,100b) in __copy_user_intel()
167 _ASM_EXTABLE(8b,100b) in __copy_user_intel()
[all …]
|
| D | copy_user_nocache_64.S | 34 jnz 100b
41 _ASM_EXTABLE(100b,103b)
42 _ASM_EXTABLE(101b,103b)
79 jnz 1b
89 jnz 18b
98 jnz 21b
115 _ASM_EXTABLE(1b,30b)
116 _ASM_EXTABLE(2b,30b)
117 _ASM_EXTABLE(3b,30b)
118 _ASM_EXTABLE(4b,30b)
[all …]
|
| D | copy_user_64.S | 36 .long \alt1-1b /* offset */ /* or alternatively to alt1 */
38 .long \alt2-1b /* offset */ /* or alternatively to alt2 */
42 altinstruction_entry 0b,2b,\feature1,5,5
43 altinstruction_entry 0b,3b,\feature2,5,5
61 jnz 100b
68 _ASM_EXTABLE(100b,103b)
69 _ASM_EXTABLE(101b,103b)
161 jnz 1b
171 jnz 18b
180 jnz 21b
[all …]
|
| /arch/arm64/crypto/ |
| D | aes-neon.S | 27 movi v12.16b, #0x40
29 movi v14.16b, #0x1b
30 ld1 {v16.16b-v19.16b}, [\temp], #64
31 ld1 {v20.16b-v23.16b}, [\temp], #64
32 ld1 {v24.16b-v27.16b}, [\temp], #64
33 ld1 {v28.16b-v31.16b}, [\temp]
52 sub v9.16b, \in\().16b, v12.16b
53 tbl \in\().16b, {v16.16b-v19.16b}, \in\().16b
54 sub v10.16b, v9.16b, v12.16b
55 tbx \in\().16b, {v20.16b-v23.16b}, v9.16b
[all …]
|
| D | aes-ce-ccm-core.S | 25 eor v1.16b, v1.16b, v1.16b
29 ins v1.b[0], w7
30 ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
32 cbnz w8, 0b
33 eor v0.16b, v0.16b, v1.16b
41 mov v5.16b, v3.16b
42 b 4f
43 2: mov v4.16b, v3.16b
45 3: aese v0.16b, v4.16b
46 aesmc v0.16b, v0.16b
[all …]
|
| D | aes-modes.S | 124 ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 pt blocks */
126 st1 {v0.16b-v1.16b}, [x0], #32
128 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
130 st1 {v0.16b-v3.16b}, [x0], #64
132 b .LecbencloopNx
138 ld1 {v0.16b}, [x1], #16 /* get next pt block */
140 st1 {v0.16b}, [x0], #16
160 ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 ct blocks */
162 st1 {v0.16b-v1.16b}, [x0], #32
164 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
[all …]
|
| D | ghash-ce-core.S | 32 ld1 {SHASH.16b}, [x3]
33 ld1 {XL.16b}, [x1]
34 movi MASK.16b, #0xe1
35 ext SHASH2.16b, SHASH.16b, SHASH.16b, #8
37 eor SHASH2.16b, SHASH2.16b, SHASH.16b
42 b 1f
48 CPU_LE( rev64 T1.16b, T1.16b )
50 ext T2.16b, XL.16b, XL.16b, #8
51 ext IN1.16b, T1.16b, T1.16b, #8
52 eor T1.16b, T1.16b, T2.16b
[all …]
|
| D | aes-ce.S | 24 ld1 {v17.16b-v18.16b}, [\rk], #32
25 1111: ld1 {v19.16b-v20.16b}, [\rk], #32
26 2222: ld1 {v21.16b-v24.16b}, [\rk], #64
27 ld1 {v25.16b-v28.16b}, [\rk], #64
28 ld1 {v29.16b-v31.16b}, [\rk]
47 aes\de \i0\().16b, \k\().16b
49 aes\de \i1\().16b, \k\().16b
51 aes\de \i2\().16b, \k\().16b
52 aes\de \i3\().16b, \k\().16b
55 aes\mc \i0\().16b, \i0\().16b
[all …]
|
| /arch/powerpc/lib/ |
| D | copyuser_64.S | 17 b __copy_tofrom_user_power7
77 bdnz 21b
128 b 2f
155 bdnz 1b
207 b .Ldst_aligned
242 b 1f
293 bdnz 43b
309 bne 1b
318 bdnz 91b
323 bdnz 92b
[all …]
|
| D | copy_32.S | 47 b 104f; \
50 b 105f; \
53 .long 8 ## n ## 0b,9 ## n ## 0b; \
54 .long 8 ## n ## 1b,9 ## n ## 0b; \
55 .long 8 ## n ## 2b,9 ## n ## 0b; \
56 .long 8 ## n ## 3b,9 ## n ## 0b; \
57 .long 8 ## n ## 4b,9 ## n ## 1b; \
58 .long 8 ## n ## 5b,9 ## n ## 1b; \
59 .long 8 ## n ## 6b,9 ## n ## 1b; \
60 .long 8 ## n ## 7b,9 ## n ## 1b; \
[all …]
|
| /arch/arm/mach-msm/include/mach/ |
| D | iommu_hw-8xxx.h | 33 #define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v)) argument
34 #define GET_GLOBAL_REG_N(b, n, r) GET_GLOBAL_REG(b, ((r) + (n << 2))) argument
37 #define GET_GLOBAL_FIELD(b, r, F) GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT) argument
38 #define GET_CONTEXT_FIELD(b, c, r, F) \ argument
39 GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)
41 #define SET_GLOBAL_FIELD(b, r, F, v) \ argument
42 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
43 #define SET_CONTEXT_FIELD(b, c, r, F, v) \ argument
44 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
97 #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) argument
[all …]
|
| /arch/hexagon/mm/ |
| D | copy_to_user.S | 81 .long 1100b,1109b
82 .long 2100b,2109b
83 .long 4100b,4109b
84 .long 8180b,8189b
85 .long 8190b,8199b
86 .long 4180b,4189b
87 .long 4190b,4199b
88 .long 2180b,2189b
89 .long 2190b,2199b
90 .long 1180b,1189b
[all …]
|
| D | copy_from_user.S | 107 .long 1000b,1009b
108 .long 2000b,2009b
109 .long 4000b,4009b
110 .long 8080b,8089b
111 .long 4080b,4089b
112 .long 2080b,2089b
113 .long 1080b,1089b
|
| /arch/avr32/lib/ |
| D | copy_user.S | 56 brge 2b
67 21: st.b r12++, r8
71 23: st.b r12++, r8
75 25: st.b r12++, r8
80 brlt 4b
84 31: st.b r12++, r8
87 breq 1b
89 33: st.b r12++, r8
92 breq 1b
94 35: st.b r12++, r8
[all …]
|
| D | clear_user.S | 33 brge 10b
44 12: st.b r12++, r8
49 brlt 2b
53 13: st.b r12++, r8
55 14: st.b r12++, r8
57 15: st.b r12++, r8
59 rjmp 1b
71 .long 10b, 18b
72 .long 11b, 19b
73 .long 12b, 19b
[all …]
|
| /arch/x86/xen/ |
| D | multicalls.c | 57 struct mc_buffer *b = &__get_cpu_var(mc_buffer); in xen_mc_flush() local
69 trace_xen_mc_flush(b->mcidx, b->argidx, b->cbidx); in xen_mc_flush()
71 switch (b->mcidx) { in xen_mc_flush()
74 BUG_ON(b->argidx != 0); in xen_mc_flush()
80 mc = &b->entries[0]; in xen_mc_flush()
90 memcpy(b->debug, b->entries, in xen_mc_flush()
91 b->mcidx * sizeof(struct multicall_entry)); in xen_mc_flush()
94 if (HYPERVISOR_multicall(b->entries, b->mcidx) != 0) in xen_mc_flush()
96 for (i = 0; i < b->mcidx; i++) in xen_mc_flush()
97 if (b->entries[i].result < 0) in xen_mc_flush()
[all …]
|
| /arch/powerpc/include/asm/ |
| D | ppc_asm.h | 113 #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b argument
114 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) argument
115 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) argument
116 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) argument
117 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) argument
118 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) argument
119 #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b argument
120 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) argument
121 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) argument
122 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) argument
[all …]
|
| D | ppc-opcode.h | 196 #define ___PPC_RB(b) (((b) & 0x1f) << 11) argument
201 #define __PPC_RB(b) ___PPC_RB(__REG_##b) argument
205 #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4)) argument
228 #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ argument
229 __PPC_RA(a) | __PPC_RB(b))
230 #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ argument
231 __PPC_RA(a) | __PPC_RB(b))
232 #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ argument
234 ___PPC_RB(b) | __PPC_EH(eh))
235 #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ argument
[all …]
|
| /arch/s390/lib/ |
| D | uaccess_std.c | 65 EX_TABLE(0b,3b) EX_TABLE(2b,3b) EX_TABLE(4b,5b) in copy_from_user_std()
66 EX_TABLE(10b,3b) EX_TABLE(11b,3b) EX_TABLE(12b,5b) in copy_from_user_std()
105 EX_TABLE(0b,3b) EX_TABLE(2b,3b) EX_TABLE(4b,6b) in copy_to_user_std()
106 EX_TABLE(7b,3b) EX_TABLE(8b,3b) EX_TABLE(9b,6b) in copy_to_user_std()
145 EX_TABLE(1b,6b) EX_TABLE(2b,0b) EX_TABLE(4b,0b) in copy_in_user_std()
180 EX_TABLE(1b,6b) EX_TABLE(2b,0b) EX_TABLE(4b,0b) in clear_user_std()
203 EX_TABLE(0b,1b) in strnlen_user_std()
238 EX_TABLE(0b,4b) EX_TABLE(2b,4b) EX_TABLE(3b,4b) \
286 EX_TABLE(0b,2b) EX_TABLE(1b,2b) in futex_atomic_cmpxchg_std()
|
| /arch/x86/kernel/cpu/mcheck/ |
| D | mce_amd.c | 69 struct threshold_block *b; member
82 static const char * const bank4_names(struct threshold_block *b) in bank4_names() argument
84 switch (b->address) { in bank4_names()
96 WARN(1, "Funny MSR: 0x%08x\n", b->address); in bank4_names()
117 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) in lvt_off_valid() argument
123 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, in lvt_off_valid()
124 b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
131 b->cpu, apic, b->bank, b->block, b->address, hi, lo); in lvt_off_valid()
147 rdmsr(tr->b->address, lo, hi); in threshold_restart_bank()
149 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) in threshold_restart_bank()
[all …]
|
| /arch/sparc/crypto/ |
| D | opcodes.h | 17 #define CRC32C(a,b,c) \ argument
18 .word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c));
29 #define AES_EROUND01(a,b,c,d) \ argument
30 .word (F3F(2, 0x19, 0)|RS1(a)|RS2(b)|RS3(c)|RD(d));
31 #define AES_EROUND23(a,b,c,d) \ argument
32 .word (F3F(2, 0x19, 1)|RS1(a)|RS2(b)|RS3(c)|RD(d));
33 #define AES_DROUND01(a,b,c,d) \ argument
34 .word (F3F(2, 0x19, 2)|RS1(a)|RS2(b)|RS3(c)|RD(d));
35 #define AES_DROUND23(a,b,c,d) \ argument
36 .word (F3F(2, 0x19, 3)|RS1(a)|RS2(b)|RS3(c)|RD(d));
[all …]
|
| /arch/x86/mm/kmemcheck/ |
| D | opcode.c | 5 static bool opcode_is_prefix(uint8_t b) in opcode_is_prefix() argument
9 b == 0xf0 || b == 0xf2 || b == 0xf3 in opcode_is_prefix()
11 || b == 0x2e || b == 0x36 || b == 0x3e || b == 0x26 in opcode_is_prefix()
12 || b == 0x64 || b == 0x65 in opcode_is_prefix()
14 || b == 0x66 in opcode_is_prefix()
16 || b == 0x67; in opcode_is_prefix()
20 static bool opcode_is_rex_prefix(uint8_t b) in opcode_is_rex_prefix() argument
22 return (b & 0xf0) == 0x40; in opcode_is_rex_prefix()
25 static bool opcode_is_rex_prefix(uint8_t b) in opcode_is_rex_prefix() argument
|
| /arch/sparc/kernel/ |
| D | una_asm_32.S | 45 b 0f
52 b 0f
61 .word 4b, retl_efault
62 .word 5b, retl_efault
63 .word 6b, retl_efault
64 .word 7b, retl_efault
65 .word 8b, retl_efault
66 .word 9b, retl_efault
67 .word 10b, retl_efault
68 .word 11b, retl_efault
[all …]
|
| D | sys32.S | 244 .word 1b, __retl_efault, 2b, __retl_efault
245 .word 3b, __retl_efault, 4b, __retl_efault
246 .word 5b, __retl_efault, 6b, __retl_efault
247 .word 7b, __retl_efault, 8b, __retl_efault
248 .word 9b, __retl_efault, 10b, __retl_efault
249 .word 11b, __retl_efault, 12b, __retl_efault
250 .word 13b, __retl_efault, 14b, __retl_efault
251 .word 15b, __retl_efault, 16b, __retl_efault
252 .word 17b, __retl_efault, 18b, __retl_efault
253 .word 19b, __retl_efault, 20b, __retl_efault
[all …]
|
| /arch/arm/mm/ |
| D | abort-lv4t.S | 35 /* 0 */ b .data_arm_lateldrhpost @ ldrh rd, [rn], #m/rm
36 /* 1 */ b .data_arm_lateldrhpre @ ldrh rd, [rn, #m/rm]
37 /* 2 */ b .data_unknown
38 /* 3 */ b .data_unknown
39 /* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
40 /* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
41 /* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
42 /* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
43 /* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
44 /* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
[all …]
|