Searched refs:bfin_read32 (Results 1 – 25 of 37) sorted by relevance
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17 #define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS)19 #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)21 #define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)23 #define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR)28 #define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)30 #define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)32 #define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)34 #define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)36 #define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)38 #define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)[all …]
113 u32 ctrl = bfin_read32(mmr) & ~mask; in _disable_cplb()121 u32 ctrl = bfin_read32(mmr) & ~mask; in disable_cplb()133 u32 ctrl = bfin_read32(mmr) | mask; in _enable_cplb()141 u32 ctrl = bfin_read32(mmr) | mask; in enable_cplb()
279 #define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)280 #define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)281 #define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)291 __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \296 #define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)309 #define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
452 if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK)) in init_cgu()456 while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) || in init_cgu()457 !(bfin_read32(CGU0_STAT) & PLOCK)) in init_cgu()462 while (bfin_read32(CGU0_STAT) & CLKSALGN) in init_cgu()
15 #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)17 #define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)19 #define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)21 #define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)23 #define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)25 #define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)27 #define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)29 #define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)31 #define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)33 #define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)[all …]
21 #define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF)23 #define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1)25 #define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2)27 #define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3)29 #define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND)31 #define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR)33 #define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET)35 #define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO)37 #define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI)39 #define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO)[all …]
19 #define bfin_read_CHIPID() bfin_read32(CHIPID)29 #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)31 #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)33 #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))36 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)38 #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)40 #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)42 #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)45 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)47 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))[all …]
19 #define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)25 #define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)27 #define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)29 #define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)31 #define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)33 #define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)41 #define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)45 #define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)47 #define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)53 #define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
19 #define bfin_read_CHIPID() bfin_read32(CHIPID)26 #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)28 #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)30 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)32 #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)34 #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)36 #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)38 #define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)40 #define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)46 #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)[all …]
16 #define bfin_read_CHIPID() bfin_read32(CHIPID)22 #define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL)24 #define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID)26 #define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL)29 #define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL)32 #define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8))35 #define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8))39 #define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)45 #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)47 #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)[all …]
20 #define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)22 #define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)24 #define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)26 #define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)28 #define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)30 #define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)40 #define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)44 #define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)49 #define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)51 #define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)[all …]
27 #define bfin_read_CHIPID() bfin_read32(CHIPID)39 #define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)41 #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)43 #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)45 #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)47 #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))50 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)52 #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)54 #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)56 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))[all …]
19 #define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)21 #define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)23 #define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)27 #define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)29 #define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)31 #define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)35 #define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)37 #define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)39 #define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)48 #define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)[all …]
15 #define bfin_read_MXVR_PLL_CTL_0() bfin_read32(MXVR_PLL_CTL_0)17 #define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)19 #define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)21 #define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)23 #define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)25 #define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)27 #define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)37 #define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)41 #define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)43 #define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)[all …]
20 #define bfin_read_CHIPID() bfin_read32(CHIPID)28 #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)30 #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)32 #define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + x * (SIC_IMASK1 - SIC_IMASK0))34 #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)36 #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)38 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))40 #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)42 #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)44 #define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + x * (SIC_IWR1 - SIC_IWR0))[all …]
23 #define bfin_read_CHIPID() bfin_read32(CHIPID)32 #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)34 #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)36 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)38 #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)40 #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)42 #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)44 #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)46 #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)48 #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)[all …]
32 #define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))34 #define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))36 #define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))38 #define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
37 *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF); in bfin_iwr_save()38 *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF); in bfin_iwr_save()
16 #define bfin_read_CHIPID() bfin_read32(CHIPID)26 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)28 #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)30 #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)32 #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)34 #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)36 #define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)38 #define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)44 #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)46 #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)[all …]
70 val2 = bfin_read32(reg); in clk_reg_write_mask()80 val = bfin_read32(reg); in clk_reg_set_bits()89 val = bfin_read32(reg); in clk_reg_clear_bits()97 while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN)); in wait_for_pll_align()99 if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) { in wait_for_pll_align()159 u32 ctl = bfin_read32(CGU0_CTL); in pll_get_rate()160 u32 stat = bfin_read32(CGU0_STAT); in pll_get_rate()179 u32 stat = bfin_read32(CGU0_STAT); in pll_set_rate()206 u32 ctl = bfin_read32(CGU0_CTL); in sys_clk_get_rate()207 u32 div = bfin_read32(CGU0_DIV); in sys_clk_get_rate()[all …]
149 while (bfin_read32(CGU0_STAT) & CLKSALGN) in bf609_ddr_sr_exit()159 while ((bfin_read32(DPM0_STAT) & 0xf) != 1); in bf609_resume_ccbuf()174 bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4); in bfin_hibernate_syscontrol()319 bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT)); in dpm0_isr()320 bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT)); in dpm0_isr()