| /arch/powerpc/platforms/cell/ |
| D | beat_spu_priv1.c | 27 static inline void _int_mask_set(struct spu *spu, int class, u64 mask) in _int_mask_set() argument
29 spu->shadow_int_mask_RW[class] = mask; in _int_mask_set()
30 beat_set_irq_mask_for_spe(spu->spe_id, class, mask); in _int_mask_set()
33 static inline u64 _int_mask_get(struct spu *spu, int class) in _int_mask_get() argument
35 return spu->shadow_int_mask_RW[class]; in _int_mask_get()
38 static void int_mask_set(struct spu *spu, int class, u64 mask) in int_mask_set() argument
40 _int_mask_set(spu, class, mask); in int_mask_set()
43 static u64 int_mask_get(struct spu *spu, int class) in int_mask_get() argument
45 return _int_mask_get(spu, class); in int_mask_get()
48 static void int_mask_and(struct spu *spu, int class, u64 mask) in int_mask_and() argument
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| D | spu_priv1_mmio.c | 39 static void int_mask_and(struct spu *spu, int class, u64 mask) in int_mask_and() argument
43 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_and()
44 out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); in int_mask_and()
47 static void int_mask_or(struct spu *spu, int class, u64 mask) in int_mask_or() argument
51 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_or()
52 out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); in int_mask_or()
55 static void int_mask_set(struct spu *spu, int class, u64 mask) in int_mask_set() argument
57 out_be64(&spu->priv1->int_mask_RW[class], mask); in int_mask_set()
60 static u64 int_mask_get(struct spu *spu, int class) in int_mask_get() argument
62 return in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_get()
[all …]
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| /arch/powerpc/include/asm/ |
| D | spu_priv1.h | 32 void (*int_mask_and) (struct spu *spu, int class, u64 mask);
33 void (*int_mask_or) (struct spu *spu, int class, u64 mask);
34 void (*int_mask_set) (struct spu *spu, int class, u64 mask);
35 u64 (*int_mask_get) (struct spu *spu, int class);
36 void (*int_stat_clear) (struct spu *spu, int class, u64 stat);
37 u64 (*int_stat_get) (struct spu *spu, int class);
57 spu_int_mask_and (struct spu *spu, int class, u64 mask) in spu_int_mask_and() argument
59 spu_priv1_ops->int_mask_and(spu, class, mask); in spu_int_mask_and()
63 spu_int_mask_or (struct spu *spu, int class, u64 mask) in spu_int_mask_or() argument
65 spu_priv1_ops->int_mask_or(spu, class, mask); in spu_int_mask_or()
[all …]
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| /arch/powerpc/perf/ |
| D | mpc7450-pmu.c | 157 int pmc, class; in mpc7450_get_constraint() local
161 class = mpc7450_classify_event(event); in mpc7450_get_constraint()
162 if (class < 0) in mpc7450_get_constraint()
164 if (class == 4) { in mpc7450_get_constraint()
169 mask = classbits[class][0]; in mpc7450_get_constraint()
170 value = classbits[class][1]; in mpc7450_get_constraint()
268 int i, j, class, tuse; in mpc7450_compute_mmcr() local
280 class = mpc7450_classify_event(event[i]); in mpc7450_compute_mmcr()
281 if (class < 0) in mpc7450_compute_mmcr()
283 j = n_classevent[class]++; in mpc7450_compute_mmcr()
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| /arch/arm/mach-omap2/ |
| D | omap_hwmod_2xxx_ipblock_data.c | 203 .class = &l3_hwmod_class,
210 .class = &l4_hwmod_class,
217 .class = &l4_hwmod_class,
230 .class = &mpu_hwmod_class,
237 .class = &iva_hwmod_class,
271 .class = &omap2xxx_timer_hwmod_class,
290 .class = &omap2xxx_timer_hwmod_class,
309 .class = &omap2xxx_timer_hwmod_class,
328 .class = &omap2xxx_timer_hwmod_class,
348 .class = &omap2xxx_timer_hwmod_class,
[all …]
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| D | mcbsp.c | 71 if (oh->class->rev < MCBSP_CONFIG_TYPE2) { in omap_init_mcbsp()
78 if (oh->class->rev == MCBSP_CONFIG_TYPE2) { in omap_init_mcbsp()
81 } else if (oh->class->rev == MCBSP_CONFIG_TYPE3) { in omap_init_mcbsp()
88 } else if (oh->class->rev == MCBSP_CONFIG_TYPE4) { in omap_init_mcbsp()
93 if (oh->class->rev >= MCBSP_CONFIG_TYPE3) in omap_init_mcbsp()
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| D | omap_hwmod_33xx_data.c | 48 .class = &am33xx_emif_fw_hwmod_class,
81 .class = &am33xx_emif_hwmod_class,
111 .class = &am33xx_l3_hwmod_class,
127 .class = &am33xx_l3_hwmod_class,
134 .class = &am33xx_l3_hwmod_class,
157 .class = &am33xx_l4_hwmod_class,
172 .class = &am33xx_l4_hwmod_class,
188 .class = &am33xx_l4_hwmod_class,
202 .class = &am33xx_l4_hwmod_class,
231 .class = &am33xx_mpu_hwmod_class,
[all …]
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| D | omap_hwmod.c | 263 if (!oh->class->sysc) { in _update_sysc_cache()
270 oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); in _update_sysc_cache()
272 if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) in _update_sysc_cache()
288 if (!oh->class->sysc) { in _write_sysconfig()
297 omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); in _write_sysconfig()
316 if (!oh->class->sysc || in _set_master_standbymode()
317 !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) in _set_master_standbymode()
320 if (!oh->class->sysc->sysc_fields) { in _set_master_standbymode()
325 mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; in _set_master_standbymode()
349 if (!oh->class->sysc || in _set_slave_idlemode()
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| D | omap_hwmod_3xxx_data.c | 66 .class = &l3_hwmod_class,
74 .class = &l4_hwmod_class,
81 .class = &l4_hwmod_class,
88 .class = &l4_hwmod_class,
95 .class = &l4_hwmod_class,
108 .class = &mpu_hwmod_class,
121 .class = &iva_hwmod_class,
149 .class = &omap3xxx_debugss_hwmod_class,
214 .class = &omap3xxx_timer_hwmod_class,
232 .class = &omap3xxx_timer_hwmod_class,
[all …]
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| D | omap_hwmod_44xx_data.c | 65 .class = &omap44xx_c2c_target_fw_hwmod_class,
91 .class = &omap44xx_dmm_hwmod_class,
113 .class = &omap44xx_emif_fw_hwmod_class,
134 .class = &omap44xx_l3_hwmod_class,
154 .class = &omap44xx_l3_hwmod_class,
168 .class = &omap44xx_l3_hwmod_class,
181 .class = &omap44xx_l3_hwmod_class,
203 .class = &omap44xx_l4_hwmod_class,
218 .class = &omap44xx_l4_hwmod_class,
231 .class = &omap44xx_l4_hwmod_class,
[all …]
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| D | omap_hwmod_2420_data.c | 58 .class = &iva1_hwmod_class,
77 .class = &dsp_hwmod_class,
122 .class = &i2c_class,
147 .class = &i2c_class,
161 .class = &omap2xxx_dma_hwmod_class,
177 .class = &omap2xxx_mailbox_hwmod_class,
214 .class = &omap2420_mcbsp_hwmod_class,
240 .class = &omap2420_mcbsp_hwmod_class,
285 .class = &omap2420_msdi_hwmod_class,
315 .class = &omap2_hdq1w_class,
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| D | wd_timer.c | 88 oh->class->sysc->syss_offs) in omap2_wd_timer_reset()
92 if (oh->class->sysc->srst_udelay) in omap2_wd_timer_reset()
93 udelay(oh->class->sysc->srst_udelay); in omap2_wd_timer_reset()
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| D | i2c.c | 72 if (oh->class->rev == OMAP_I2C_IP_VERSION_2) { in omap_i2c_reset()
74 } else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) { in omap_i2c_reset()
97 oh->class->sysc->syss_offs) in omap_i2c_reset()
166 pdata->rev = oh->class->rev; in omap_i2c_add_bus()
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| D | omap_hwmod_2430_data.c | 54 .class = &iva_hwmod_class,
108 .class = &i2c_class,
128 .class = &i2c_class,
152 .class = &omap2xxx_gpio_hwmod_class,
165 .class = &omap2xxx_dma_hwmod_class,
180 .class = &omap2xxx_mailbox_hwmod_class,
226 .class = &omap2xxx_mcspi_class,
269 .class = &usbotg_class,
313 .class = &omap2430_mcbsp_hwmod_class,
340 .class = &omap2430_mcbsp_hwmod_class,
[all …]
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| /arch/avr32/boards/merisc/ |
| D | merisc_sysfs.c | 21 static ssize_t merisc_model_show(struct class *class, char *buf) in merisc_model_show() argument
31 static ssize_t merisc_revision_show(struct class *class, char *buf) in merisc_revision_show() argument
47 struct class merisc_class = {
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| /arch/alpha/kernel/ |
| D | err_common.c | 95 if (header->class != EL_CLASS__HEADER) { in el_process_header_subpacket()
98 header->class, header->type); in el_process_header_subpacket()
133 header->class, header->type); in el_process_header_subpacket()
141 header->class, header->type); in el_process_header_subpacket()
161 for (; h && h->class != header->class; h = h->next); in el_process_subpacket_reg()
198 switch(header->class) { in el_process_subpacket()
210 header->class, header->type); in el_process_subpacket()
225 if (a->class == header->class && in el_annotate_subpacket()
251 for (err = 0; header && (header->class != EL_CLASS__TERMINATION); err++) in cdl_process_console_data_log()
286 if ((a->class == new->class && a->type == new->type) || in cdl_register_subpacket_annotation()
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| D | err_ev7.c | 32 if (el_ptr->class != EL_CLASS__HEADER || in ev7_collect_logout_frame_subpackets()
45 if (el_ptr->class != EL_CLASS__PAL || in ev7_collect_logout_frame_subpackets()
64 if (subpacket->class != EL_CLASS__PAL) { in ev7_collect_logout_frame_subpackets()
67 err_print_prefix, subpacket->class, i); in ev7_collect_logout_frame_subpackets()
238 if (header->class != EL_CLASS__PAL) { in ev7_process_pal_subpacket()
241 header->class, header->type); in ev7_process_pal_subpacket()
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| D | pci.c | 64 dev->class = PCI_CLASS_BRIDGE_ISA << 8; in quirk_isa_bridge()
75 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) { in quirk_cypress()
93 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) { in quirk_cypress()
109 unsigned int class = dev->class >> 8; in pcibios_fixup_final() local
111 if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) { in pcibios_fixup_final()
248 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { in pcibios_fixup_bus()
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| /arch/frv/mb93090-mb00/ |
| D | pci-frv.c | 154 int class = dev->class >> 8; in pcibios_assign_resources() local
157 if (!class || class == PCI_CLASS_BRIDGE_HOST) in pcibios_assign_resources()
166 if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) || in pcibios_assign_resources()
167 (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO))) in pcibios_assign_resources()
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| /arch/powerpc/platforms/ps3/ |
| D | spu.c | 479 static void int_mask_and(struct spu *spu, int class, u64 mask) in int_mask_and() argument
484 old_mask = spu_int_mask_get(spu, class); in int_mask_and()
485 spu_int_mask_set(spu, class, old_mask & mask); in int_mask_and()
488 static void int_mask_or(struct spu *spu, int class, u64 mask) in int_mask_or() argument
492 old_mask = spu_int_mask_get(spu, class); in int_mask_or()
493 spu_int_mask_set(spu, class, old_mask | mask); in int_mask_or()
496 static void int_mask_set(struct spu *spu, int class, u64 mask) in int_mask_set() argument
498 spu_pdata(spu)->cache.masks[class] = mask; in int_mask_set()
499 lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class, in int_mask_set()
500 spu_pdata(spu)->cache.masks[class]); in int_mask_set()
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| /arch/mips/include/asm/ |
| D | mips_mt.h | 23 struct class;
24 extern struct class *mt_class;
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| /arch/powerpc/kernel/ |
| D | pci_dn.c | 102 u32 class; in traverse_pci_devices() local
106 class = classp ? *classp : 0; in traverse_pci_devices()
112 if (dn->child && ((class >> 8) == PCI_CLASS_BRIDGE_PCI || in traverse_pci_devices()
113 (class >> 8) == PCI_CLASS_BRIDGE_CARDBUS)) in traverse_pci_devices()
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| /arch/x86/ia32/ |
| D | Makefile | 10 audit-class-$(CONFIG_AUDIT) := audit.o
11 obj-$(CONFIG_IA32_EMULATION) += $(audit-class-y)
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| /arch/x86/kernel/ |
| D | early-quirks.c | 217 u32 class; member
260 u16 class; in check_dev_quirk() local
266 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE); in check_dev_quirk()
268 if (class == 0xffff) in check_dev_quirk()
280 (!((early_qrk[i].class ^ class) & in check_dev_quirk()
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| /arch/mips/pci/ |
| D | fixup-emma2rh.c | 75 dev->class &= 0xff; in emma2rh_pci_host_fixup()
76 dev->class |= PCI_CLASS_BRIDGE_HOST << 8; in emma2rh_pci_host_fixup()
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