1 /* 2 * Based on arch/arm/include/asm/ptrace.h 3 * 4 * Copyright (C) 1996-2003 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_PTRACE_H 20 #define __ASM_PTRACE_H 21 22 #include <uapi/asm/ptrace.h> 23 24 /* AArch32-specific ptrace requests */ 25 #define COMPAT_PTRACE_GETREGS 12 26 #define COMPAT_PTRACE_SETREGS 13 27 #define COMPAT_PTRACE_GET_THREAD_AREA 22 28 #define COMPAT_PTRACE_SET_SYSCALL 23 29 #define COMPAT_PTRACE_GETVFPREGS 27 30 #define COMPAT_PTRACE_SETVFPREGS 28 31 #define COMPAT_PTRACE_GETHBPREGS 29 32 #define COMPAT_PTRACE_SETHBPREGS 30 33 34 /* AArch32 CPSR bits */ 35 #define COMPAT_PSR_MODE_MASK 0x0000001f 36 #define COMPAT_PSR_MODE_USR 0x00000010 37 #define COMPAT_PSR_MODE_FIQ 0x00000011 38 #define COMPAT_PSR_MODE_IRQ 0x00000012 39 #define COMPAT_PSR_MODE_SVC 0x00000013 40 #define COMPAT_PSR_MODE_ABT 0x00000017 41 #define COMPAT_PSR_MODE_HYP 0x0000001a 42 #define COMPAT_PSR_MODE_UND 0x0000001b 43 #define COMPAT_PSR_MODE_SYS 0x0000001f 44 #define COMPAT_PSR_T_BIT 0x00000020 45 #define COMPAT_PSR_F_BIT 0x00000040 46 #define COMPAT_PSR_I_BIT 0x00000080 47 #define COMPAT_PSR_A_BIT 0x00000100 48 #define COMPAT_PSR_E_BIT 0x00000200 49 #define COMPAT_PSR_J_BIT 0x01000000 50 #define COMPAT_PSR_Q_BIT 0x08000000 51 #define COMPAT_PSR_V_BIT 0x10000000 52 #define COMPAT_PSR_C_BIT 0x20000000 53 #define COMPAT_PSR_Z_BIT 0x40000000 54 #define COMPAT_PSR_N_BIT 0x80000000 55 #define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 56 /* 57 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 58 * process is located in memory. 59 */ 60 #define COMPAT_PT_TEXT_ADDR 0x10000 61 #define COMPAT_PT_DATA_ADDR 0x10004 62 #define COMPAT_PT_TEXT_END_ADDR 0x10008 63 64 /* 65 * used to skip a system call when tracer changes its number to -1 66 * with ptrace(PTRACE_SET_SYSCALL) 67 */ 68 #define RET_SKIP_SYSCALL -1 69 #define RET_SKIP_SYSCALL_TRACE -2 70 #define IS_SKIP_SYSCALL(no) ((int)(no & 0xffffffff) == -1) 71 72 #ifndef __ASSEMBLY__ 73 74 /* sizeof(struct user) for AArch32 */ 75 #define COMPAT_USER_SZ 296 76 77 /* Architecturally defined mapping between AArch32 and AArch64 registers */ 78 #define compat_usr(x) regs[(x)] 79 #define compat_fp regs[11] 80 #define compat_sp regs[13] 81 #define compat_lr regs[14] 82 #define compat_sp_hyp regs[15] 83 #define compat_sp_irq regs[16] 84 #define compat_lr_irq regs[17] 85 #define compat_sp_svc regs[18] 86 #define compat_lr_svc regs[19] 87 #define compat_sp_abt regs[20] 88 #define compat_lr_abt regs[21] 89 #define compat_sp_und regs[22] 90 #define compat_lr_und regs[23] 91 #define compat_r8_fiq regs[24] 92 #define compat_r9_fiq regs[25] 93 #define compat_r10_fiq regs[26] 94 #define compat_r11_fiq regs[27] 95 #define compat_r12_fiq regs[28] 96 #define compat_sp_fiq regs[29] 97 #define compat_lr_fiq regs[30] 98 99 /* 100 * This struct defines the way the registers are stored on the stack during an 101 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for 102 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. 103 */ 104 struct pt_regs { 105 union { 106 struct user_pt_regs user_regs; 107 struct { 108 u64 regs[31]; 109 u64 sp; 110 u64 pc; 111 u64 pstate; 112 }; 113 }; 114 u64 orig_x0; 115 u64 syscallno; 116 }; 117 118 #define arch_has_single_step() (1) 119 120 #ifdef CONFIG_COMPAT 121 #define compat_thumb_mode(regs) \ 122 (((regs)->pstate & COMPAT_PSR_T_BIT)) 123 #else 124 #define compat_thumb_mode(regs) (0) 125 #endif 126 127 #define user_mode(regs) \ 128 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) 129 130 #define compat_user_mode(regs) \ 131 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ 132 (PSR_MODE32_BIT | PSR_MODE_EL0t)) 133 134 #define processor_mode(regs) \ 135 ((regs)->pstate & PSR_MODE_MASK) 136 137 #define interrupts_enabled(regs) \ 138 (!((regs)->pstate & PSR_I_BIT)) 139 140 #define fast_interrupts_enabled(regs) \ 141 (!((regs)->pstate & PSR_F_BIT)) 142 143 #define user_stack_pointer(regs) \ 144 (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp) 145 regs_return_value(struct pt_regs * regs)146static inline unsigned long regs_return_value(struct pt_regs *regs) 147 { 148 return regs->regs[0]; 149 } 150 151 /* 152 * Are the current registers suitable for user mode? (used to maintain 153 * security in signal handlers) 154 */ valid_user_regs(struct user_pt_regs * regs)155static inline int valid_user_regs(struct user_pt_regs *regs) 156 { 157 if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) { 158 regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT); 159 160 /* The T bit is reserved for AArch64 */ 161 if (!(regs->pstate & PSR_MODE32_BIT)) 162 regs->pstate &= ~COMPAT_PSR_T_BIT; 163 164 return 1; 165 } 166 167 /* 168 * Force PSR to something logical... 169 */ 170 regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \ 171 COMPAT_PSR_T_BIT | PSR_MODE32_BIT; 172 173 if (!(regs->pstate & PSR_MODE32_BIT)) { 174 regs->pstate &= ~COMPAT_PSR_T_BIT; 175 regs->pstate |= PSR_MODE_EL0t; 176 } 177 178 return 0; 179 } 180 181 #define instruction_pointer(regs) ((unsigned long)(regs)->pc) 182 183 #ifdef CONFIG_SMP 184 extern unsigned long profile_pc(struct pt_regs *regs); 185 #else 186 #define profile_pc(regs) instruction_pointer(regs) 187 #endif 188 189 /* 190 * True if instr is a 32-bit thumb instruction. This works if instr 191 * is the first or only half-word of a thumb instruction. It also works 192 * when instr holds all 32-bits of a wide thumb instruction if stored 193 * in the form (first_half<<16)|(second_half) 194 */ 195 #define is_wide_instruction(instr) ((unsigned)(instr) >= 0xe800) 196 197 #endif /* __ASSEMBLY__ */ 198 #endif 199