| /arch/alpha/kernel/ |
| D | perf_event.c | 381 static void maybe_change_configuration(struct cpu_hw_events *cpuc) in maybe_change_configuration() argument
385 if (cpuc->n_added == 0) in maybe_change_configuration()
389 for (j = 0; j < cpuc->n_events; j++) { in maybe_change_configuration()
390 struct perf_event *pe = cpuc->event[j]; in maybe_change_configuration()
392 if (cpuc->current_idx[j] != PMC_NO_INDEX && in maybe_change_configuration()
393 cpuc->current_idx[j] != pe->hw.idx) { in maybe_change_configuration()
394 alpha_perf_event_update(pe, &pe->hw, cpuc->current_idx[j], 0); in maybe_change_configuration()
395 cpuc->current_idx[j] = PMC_NO_INDEX; in maybe_change_configuration()
400 cpuc->idx_mask = 0; in maybe_change_configuration()
401 for (j = 0; j < cpuc->n_events; j++) { in maybe_change_configuration()
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| /arch/x86/kernel/cpu/ |
| D | perf_event_intel_lbr.c | 109 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
119 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in __intel_pmu_lbr_enable() local
121 if (cpuc->lbr_sel) in __intel_pmu_lbr_enable()
122 wrmsrl(MSR_LBR_SELECT, cpuc->lbr_sel->config); in __intel_pmu_lbr_enable()
169 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in intel_pmu_lbr_enable() local
178 if (event->ctx->task && cpuc->lbr_context != event->ctx) { in intel_pmu_lbr_enable()
180 cpuc->lbr_context = event->ctx; in intel_pmu_lbr_enable()
182 cpuc->br_sel = event->hw.branch_reg.reg; in intel_pmu_lbr_enable()
184 cpuc->lbr_users++; in intel_pmu_lbr_enable()
189 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in intel_pmu_lbr_disable() local
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| D | perf_event_amd.c | 207 static inline int amd_has_nb(struct cpu_hw_events *cpuc) in amd_has_nb() argument
209 struct amd_nb *nb = cpuc->amd_nb; in amd_has_nb()
235 static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc, in __amd_put_nb_event_constraints() argument
238 struct amd_nb *nb = cpuc->amd_nb; in __amd_put_nb_event_constraints()
292 __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, in __amd_get_nb_event_constraints() argument
296 struct amd_nb *nb = cpuc->amd_nb; in __amd_get_nb_event_constraints()
303 if (cpuc->is_fake) in __amd_get_nb_event_constraints()
369 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); in amd_pmu_cpu_prepare() local
371 WARN_ON_ONCE(cpuc->amd_nb); in amd_pmu_cpu_prepare()
376 cpuc->amd_nb = amd_alloc_nb(cpu); in amd_pmu_cpu_prepare()
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| D | perf_event.c | 495 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in x86_pmu_disable_all() local
501 if (!test_bit(idx, cpuc->active_mask)) in x86_pmu_disable_all()
513 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in x86_pmu_disable() local
518 if (!cpuc->enabled) in x86_pmu_disable()
521 cpuc->n_added = 0; in x86_pmu_disable()
522 cpuc->enabled = 0; in x86_pmu_disable()
530 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in x86_pmu_enable_all() local
534 struct hw_perf_event *hwc = &cpuc->events[idx]->hw; in x86_pmu_enable_all()
536 if (!test_bit(idx, cpuc->active_mask)) in x86_pmu_enable_all()
725 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) in x86_schedule_events() argument
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| D | perf_event_intel.c | 883 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in intel_pmu_disable_all() local
887 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) in intel_pmu_disable_all()
896 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in intel_pmu_enable_all() local
901 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); in intel_pmu_enable_all()
903 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { in intel_pmu_enable_all()
905 cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; in intel_pmu_enable_all()
930 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in intel_pmu_nhm_workaround() local
963 event = cpuc->events[i]; in intel_pmu_nhm_workaround()
977 event = cpuc->events[i]; in intel_pmu_nhm_workaround()
1024 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in intel_pmu_disable_event() local
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| D | perf_event_intel_ds.c | 398 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in intel_pmu_disable_bts() local
401 if (!cpuc->ds) in intel_pmu_disable_bts()
415 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in intel_pmu_drain_bts_buffer() local
416 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_bts_buffer()
422 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; in intel_pmu_drain_bts_buffer()
572 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in intel_pmu_pebs_enable() local
577 cpuc->pebs_enabled |= 1ULL << hwc->idx; in intel_pmu_pebs_enable()
580 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); in intel_pmu_pebs_enable()
582 cpuc->pebs_enabled |= 1ULL << 63; in intel_pmu_pebs_enable()
587 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in intel_pmu_pebs_disable() local
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| D | perf_event_knc.c | 215 struct cpu_hw_events *cpuc; in knc_pmu_handle_irq() local
220 cpuc = &__get_cpu_var(cpu_hw_events); in knc_pmu_handle_irq()
242 struct perf_event *event = cpuc->events[bit]; in knc_pmu_handle_irq()
246 if (!test_bit(bit, cpuc->active_mask)) in knc_pmu_handle_irq()
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| D | perf_event_p4.c | 918 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in p4_pmu_disable_all() local
922 struct perf_event *event = cpuc->events[idx]; in p4_pmu_disable_all()
923 if (!test_bit(idx, cpuc->active_mask)) in p4_pmu_disable_all()
987 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in p4_pmu_enable_all() local
991 struct perf_event *event = cpuc->events[idx]; in p4_pmu_enable_all()
992 if (!test_bit(idx, cpuc->active_mask)) in p4_pmu_enable_all()
1001 struct cpu_hw_events *cpuc; in p4_pmu_handle_irq() local
1007 cpuc = &__get_cpu_var(cpu_hw_events); in p4_pmu_handle_irq()
1012 if (!test_bit(idx, cpuc->active_mask)) { in p4_pmu_handle_irq()
1014 if (__test_and_clear_bit(idx, cpuc->running)) in p4_pmu_handle_irq()
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| D | perf_event.h | 351 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
370 (*get_event_constraints)(struct cpu_hw_events *cpuc,
373 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
533 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
602 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
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| /arch/sparc/kernel/ |
| D | perf_event.c | 818 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, in… in sparc_pmu_enable_event() argument
826 enc = perf_event_get_enc(cpuc->events[idx]); in sparc_pmu_enable_event()
828 val = cpuc->pcr[pcr_index]; in sparc_pmu_enable_event()
831 cpuc->pcr[pcr_index] = val; in sparc_pmu_enable_event()
833 pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]); in sparc_pmu_enable_event()
836 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, i… in sparc_pmu_disable_event() argument
846 val = cpuc->pcr[pcr_index]; in sparc_pmu_disable_event()
849 cpuc->pcr[pcr_index] = val; in sparc_pmu_disable_event()
851 pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]); in sparc_pmu_disable_event()
910 static void read_in_all_counters(struct cpu_hw_events *cpuc) in read_in_all_counters() argument
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| /arch/sh/kernel/ |
| D | perf_event.c | 230 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in sh_pmu_stop() local
236 cpuc->events[idx] = NULL; in sh_pmu_stop()
248 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in sh_pmu_start() local
258 cpuc->events[idx] = event; in sh_pmu_start()
265 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in sh_pmu_del() local
268 __clear_bit(event->hw.idx, cpuc->used_mask); in sh_pmu_del()
275 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in sh_pmu_add() local
282 if (__test_and_set_bit(idx, cpuc->used_mask)) { in sh_pmu_add()
283 idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events); in sh_pmu_add()
287 __set_bit(idx, cpuc->used_mask); in sh_pmu_add()
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| /arch/blackfin/kernel/ |
| D | perf_event.c | 303 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in bfin_pmu_stop() local
309 cpuc->events[idx] = NULL; in bfin_pmu_stop()
321 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in bfin_pmu_start() local
331 cpuc->events[idx] = event; in bfin_pmu_start()
338 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in bfin_pmu_del() local
341 __clear_bit(event->hw.idx, cpuc->used_mask); in bfin_pmu_del()
348 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in bfin_pmu_add() local
355 if (__test_and_set_bit(idx, cpuc->used_mask)) { in bfin_pmu_add()
356 idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS); in bfin_pmu_add()
360 __set_bit(idx, cpuc->used_mask); in bfin_pmu_add()
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| /arch/metag/kernel/perf/ |
| D | perf_event.c | 261 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in metag_pmu_start() local
288 cpuc->events[idx] = event; in metag_pmu_start()
309 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in metag_pmu_add() local
318 cpuc->used_mask)) { in metag_pmu_add()
325 idx = find_first_zero_bit(cpuc->used_mask, in metag_pmu_add()
332 __set_bit(idx, cpuc->used_mask); in metag_pmu_add()
351 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in metag_pmu_del() local
357 cpuc->events[idx] = NULL; in metag_pmu_del()
358 __clear_bit(idx, cpuc->used_mask); in metag_pmu_del()
820 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); in metag_pmu_cpu_notify() local
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| /arch/mips/kernel/ |
| D | perf_event_mipsxx.c | 311 static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, in mipsxx_pmu_alloc_counter() argument
334 !test_and_set_bit(i, cpuc->used_mask)) in mipsxx_pmu_alloc_counter()
343 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in mipsxx_pmu_enable_event() local
347 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | in mipsxx_pmu_enable_event()
353 cpuc->saved_ctrl[idx] |= in mipsxx_pmu_enable_event()
363 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in mipsxx_pmu_disable_event() local
369 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) & in mipsxx_pmu_disable_event()
371 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]); in mipsxx_pmu_disable_event()
463 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); in mipspmu_add() local
471 idx = mipsxx_pmu_alloc_counter(cpuc, hwc); in mipspmu_add()
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| /arch/arm/kernel/ |
| D | perf_event_xscale.c | 228 struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events(); in xscale1pmu_handle_irq() local
253 struct perf_event *event = cpuc->events[idx]; in xscale1pmu_handle_irq()
354 xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc, in xscale1pmu_get_event_idx() argument
359 if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask)) in xscale1pmu_get_event_idx()
364 if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) in xscale1pmu_get_event_idx()
367 if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) in xscale1pmu_get_event_idx()
575 struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events(); in xscale2pmu_handle_irq() local
594 struct perf_event *event = cpuc->events[idx]; in xscale2pmu_handle_irq()
723 xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc, in xscale2pmu_get_event_idx() argument
726 int idx = xscale1pmu_get_event_idx(cpuc, event); in xscale2pmu_get_event_idx()
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| D | perf_event_v6.c | 480 struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events(); in armv6pmu_handle_irq() local
497 struct perf_event *event = cpuc->events[idx]; in armv6pmu_handle_irq()
558 armv6pmu_get_event_idx(struct pmu_hw_events *cpuc, in armv6pmu_get_event_idx() argument
564 if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask)) in armv6pmu_get_event_idx()
573 if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) in armv6pmu_get_event_idx()
576 if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) in armv6pmu_get_event_idx()
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| D | perf_event_v7.c | 1036 struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events(); in armv7pmu_handle_irq() local
1057 struct perf_event *event = cpuc->events[idx]; in armv7pmu_handle_irq()
1115 static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc, in armv7pmu_get_event_idx() argument
1125 if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask)) in armv7pmu_get_event_idx()
1136 if (!test_and_set_bit(idx, cpuc->used_mask)) in armv7pmu_get_event_idx()
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| /arch/arm64/kernel/ |
| D | perf_event.c | 1075 struct pmu_hw_events *cpuc; in armv8pmu_handle_irq() local
1095 cpuc = &__get_cpu_var(cpu_hw_events); in armv8pmu_handle_irq()
1097 struct perf_event *event = cpuc->events[idx]; in armv8pmu_handle_irq()
1155 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, in armv8pmu_get_event_idx() argument
1163 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) in armv8pmu_get_event_idx()
1174 if (!test_and_set_bit(idx, cpuc->used_mask)) in armv8pmu_get_event_idx()
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