Searched refs:dpll_core_x2_ck (Results 1 – 2 of 2) sorted by relevance
| /arch/arm/mach-omap2/ |
| D | cclock33xx_data.c | 122 static struct clk dpll_core_x2_ck; variable
130 .clk = &dpll_core_x2_ck,
135 DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
137 DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
143 DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
149 DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
878 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
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| D | cclock44xx_data.c | 281 static struct clk dpll_core_x2_ck; variable
285 .clk = &dpll_core_x2_ck,
289 DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
292 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
303 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
319 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
350 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
363 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
1477 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
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