1 /*
2 * AM33XX Clock data
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/clk-private.h>
20 #include <linux/clkdev.h>
21 #include <linux/io.h>
22
23 #include "am33xx.h"
24 #include "soc.h"
25 #include "iomap.h"
26 #include "clock.h"
27 #include "control.h"
28 #include "cm.h"
29 #include "cm33xx.h"
30 #include "cm-regbits-33xx.h"
31 #include "prm.h"
32
33 /* Modulemode control */
34 #define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
35 #define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
36
37 /*LIST_HEAD(clocks);*/
38
39 /* Root clocks */
40
41 /* RTC 32k */
42 DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
43
44 /* On-Chip 32KHz RC OSC */
45 DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
46
47 /* Crystal input clks */
48 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
49
50 DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
51
52 DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
53
54 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
55
56 /* Oscillator clock */
57 /* 19.2, 24, 25 or 26 MHz */
58 static const char *sys_clkin_ck_parents[] = {
59 "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
60 "virt_26000000_ck",
61 };
62
63 /*
64 * sys_clk in: input to the dpll and also used as funtional clock for,
65 * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
66 *
67 */
68 DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
69 AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
70 AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
71 AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
72 0, NULL);
73
74 /* External clock - 12 MHz */
75 DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
76
77 /* Module clocks and DPLL outputs */
78
79 /* DPLL_CORE */
80 static struct dpll_data dpll_core_dd = {
81 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
82 .clk_bypass = &sys_clkin_ck,
83 .clk_ref = &sys_clkin_ck,
84 .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
85 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
86 .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
87 .mult_mask = AM33XX_DPLL_MULT_MASK,
88 .div1_mask = AM33XX_DPLL_DIV_MASK,
89 .enable_mask = AM33XX_DPLL_EN_MASK,
90 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
91 .max_multiplier = 2047,
92 .max_divider = 128,
93 .min_divider = 1,
94 };
95
96 /* CLKDCOLDO output */
97 static const char *dpll_core_ck_parents[] = {
98 "sys_clkin_ck",
99 };
100
101 static struct clk dpll_core_ck;
102
103 static const struct clk_ops dpll_core_ck_ops = {
104 .recalc_rate = &omap3_dpll_recalc,
105 .get_parent = &omap2_init_dpll_parent,
106 };
107
108 static struct clk_hw_omap dpll_core_ck_hw = {
109 .hw = {
110 .clk = &dpll_core_ck,
111 },
112 .dpll_data = &dpll_core_dd,
113 .ops = &clkhwops_omap3_dpll,
114 };
115
116 DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
117
118 static const char *dpll_core_x2_ck_parents[] = {
119 "dpll_core_ck",
120 };
121
122 static struct clk dpll_core_x2_ck;
123
124 static const struct clk_ops dpll_x2_ck_ops = {
125 .recalc_rate = &omap3_clkoutx2_recalc,
126 };
127
128 static struct clk_hw_omap dpll_core_x2_ck_hw = {
129 .hw = {
130 .clk = &dpll_core_x2_ck,
131 },
132 .flags = CLOCK_CLKOUTX2,
133 };
134
135 DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
136
137 DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
138 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
139 AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
140 AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
141 NULL);
142
143 DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
144 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
145 AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
146 AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
147 CLK_DIVIDER_ONE_BASED, NULL);
148
149 DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
150 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
151 AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
152 AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
153 CLK_DIVIDER_ONE_BASED, NULL);
154
155
156 /* DPLL_MPU */
157 static struct dpll_data dpll_mpu_dd = {
158 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
159 .clk_bypass = &sys_clkin_ck,
160 .clk_ref = &sys_clkin_ck,
161 .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
162 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
163 .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
164 .mult_mask = AM33XX_DPLL_MULT_MASK,
165 .div1_mask = AM33XX_DPLL_DIV_MASK,
166 .enable_mask = AM33XX_DPLL_EN_MASK,
167 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
168 .max_multiplier = 2047,
169 .max_divider = 128,
170 .min_divider = 1,
171 };
172
173 /* CLKOUT: fdpll/M2 */
174 static struct clk dpll_mpu_ck;
175
176 static const struct clk_ops dpll_mpu_ck_ops = {
177 .enable = &omap3_noncore_dpll_enable,
178 .disable = &omap3_noncore_dpll_disable,
179 .recalc_rate = &omap3_dpll_recalc,
180 .round_rate = &omap2_dpll_round_rate,
181 .set_rate = &omap3_noncore_dpll_set_rate,
182 .get_parent = &omap2_init_dpll_parent,
183 };
184
185 static struct clk_hw_omap dpll_mpu_ck_hw = {
186 .hw = {
187 .clk = &dpll_mpu_ck,
188 },
189 .dpll_data = &dpll_mpu_dd,
190 .ops = &clkhwops_omap3_dpll,
191 };
192
193 DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
194
195 /*
196 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
197 * and ALT_CLK1/2)
198 */
199 DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
200 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
201 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
202
203 /* DPLL_DDR */
204 static struct dpll_data dpll_ddr_dd = {
205 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
206 .clk_bypass = &sys_clkin_ck,
207 .clk_ref = &sys_clkin_ck,
208 .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
209 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
210 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
211 .mult_mask = AM33XX_DPLL_MULT_MASK,
212 .div1_mask = AM33XX_DPLL_DIV_MASK,
213 .enable_mask = AM33XX_DPLL_EN_MASK,
214 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
215 .max_multiplier = 2047,
216 .max_divider = 128,
217 .min_divider = 1,
218 };
219
220 /* CLKOUT: fdpll/M2 */
221 static struct clk dpll_ddr_ck;
222
223 static const struct clk_ops dpll_ddr_ck_ops = {
224 .recalc_rate = &omap3_dpll_recalc,
225 .get_parent = &omap2_init_dpll_parent,
226 .round_rate = &omap2_dpll_round_rate,
227 .set_rate = &omap3_noncore_dpll_set_rate,
228 };
229
230 static struct clk_hw_omap dpll_ddr_ck_hw = {
231 .hw = {
232 .clk = &dpll_ddr_ck,
233 },
234 .dpll_data = &dpll_ddr_dd,
235 .ops = &clkhwops_omap3_dpll,
236 };
237
238 DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
239
240 /*
241 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
242 * and ALT_CLK1/2)
243 */
244 DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
245 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
246 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
247 CLK_DIVIDER_ONE_BASED, NULL);
248
249 /* emif_fck functional clock */
250 DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
251 0x0, 1, 2);
252
253 /* DPLL_DISP */
254 static struct dpll_data dpll_disp_dd = {
255 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
256 .clk_bypass = &sys_clkin_ck,
257 .clk_ref = &sys_clkin_ck,
258 .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
259 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
260 .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
261 .mult_mask = AM33XX_DPLL_MULT_MASK,
262 .div1_mask = AM33XX_DPLL_DIV_MASK,
263 .enable_mask = AM33XX_DPLL_EN_MASK,
264 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
265 .max_multiplier = 2047,
266 .max_divider = 128,
267 .min_divider = 1,
268 };
269
270 /* CLKOUT: fdpll/M2 */
271 static struct clk dpll_disp_ck;
272
273 static struct clk_hw_omap dpll_disp_ck_hw = {
274 .hw = {
275 .clk = &dpll_disp_ck,
276 },
277 .dpll_data = &dpll_disp_dd,
278 .ops = &clkhwops_omap3_dpll,
279 };
280
281 DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
282
283 /*
284 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
285 * and ALT_CLK1/2)
286 */
287 DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
288 CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
289 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
290 CLK_DIVIDER_ONE_BASED, NULL);
291
292 /* DPLL_PER */
293 static struct dpll_data dpll_per_dd = {
294 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
295 .clk_bypass = &sys_clkin_ck,
296 .clk_ref = &sys_clkin_ck,
297 .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
298 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
299 .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
300 .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
301 .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
302 .enable_mask = AM33XX_DPLL_EN_MASK,
303 .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
304 .max_multiplier = 2047,
305 .max_divider = 128,
306 .min_divider = 1,
307 .flags = DPLL_J_TYPE,
308 };
309
310 /* CLKDCOLDO */
311 static struct clk dpll_per_ck;
312
313 static struct clk_hw_omap dpll_per_ck_hw = {
314 .hw = {
315 .clk = &dpll_per_ck,
316 },
317 .dpll_data = &dpll_per_dd,
318 .ops = &clkhwops_omap3_dpll,
319 };
320
321 DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
322
323 /* CLKOUT: fdpll/M2 */
324 DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
325 AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
326 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
327 NULL);
328
329 DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
330 &dpll_per_m2_ck, 0x0, 1, 4);
331
332 DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
333 &dpll_per_m2_ck, 0x0, 1, 4);
334
335 DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
336 &dpll_core_m4_ck, 0x0, 1, 2);
337
338 DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
339 1, 2);
340
341 DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
342 8);
343
344 /*
345 * Below clock nodes describes clockdomains derived out
346 * of core clock.
347 */
348 static const struct clk_ops clk_ops_null = {
349 };
350
351 static const char *l3_gclk_parents[] = {
352 "dpll_core_m4_ck"
353 };
354
355 static struct clk l3_gclk;
356 DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
357 DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
358
359 static struct clk l4hs_gclk;
360 DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
361 DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
362
363 static const char *l3s_gclk_parents[] = {
364 "dpll_core_m4_div2_ck"
365 };
366
367 static struct clk l3s_gclk;
368 DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
369 DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
370
371 static struct clk l4fw_gclk;
372 DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
373 DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
374
375 static struct clk l4ls_gclk;
376 DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
377 DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
378
379 static struct clk sysclk_div_ck;
380 DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
381 DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
382
383 /*
384 * In order to match the clock domain with hwmod clockdomain entry,
385 * separate clock nodes is required for the modules which are
386 * directly getting their funtioncal clock from sys_clkin.
387 */
388 static struct clk adc_tsc_fck;
389 DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
390 DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
391
392 static struct clk dcan0_fck;
393 DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
394 DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
395
396 static struct clk dcan1_fck;
397 DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
398 DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
399
400 static struct clk mcasp0_fck;
401 DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
402 DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
403
404 static struct clk mcasp1_fck;
405 DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
406 DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
407
408 static struct clk smartreflex0_fck;
409 DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
410 DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
411
412 static struct clk smartreflex1_fck;
413 DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
414 DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
415
416 static struct clk sha0_fck;
417 DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
418 DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
419
420 static struct clk aes0_fck;
421 DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
422 DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
423
424 /*
425 * Modules clock nodes
426 *
427 * The following clock leaf nodes are added for the moment because:
428 *
429 * - hwmod data is not present for these modules, either hwmod
430 * control is not required or its not populated.
431 * - Driver code is not yet migrated to use hwmod/runtime pm
432 * - Modules outside kernel access (to disable them by default)
433 *
434 * - debugss
435 * - mmu (gfx domain)
436 * - cefuse
437 * - usbotg_fck (its additional clock and not really a modulemode)
438 * - ieee5000
439 */
440 DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
441 AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
442 0x0, NULL);
443
444 DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
445 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
446 0x0, NULL);
447
448 DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
449 AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
450 0x0, NULL);
451
452 /*
453 * clkdiv32 is generated from fixed division of 732.4219
454 */
455 DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
456
457 static struct clk clkdiv32k_ick;
458
459 static const char *clkdiv32k_ick_parent_names[] = {
460 "clkdiv32k_ck",
461 };
462
463 static const struct clk_ops clkdiv32k_ick_ops = {
464 .enable = &omap2_dflt_clk_enable,
465 .disable = &omap2_dflt_clk_disable,
466 .is_enabled = &omap2_dflt_clk_is_enabled,
467 .init = &omap2_init_clk_clkdm,
468 };
469
470 static struct clk_hw_omap clkdiv32k_ick_hw = {
471 .hw = {
472 .clk = &clkdiv32k_ick,
473 },
474 .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
475 .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT,
476 .clkdm_name = "clk_24mhz_clkdm",
477 };
478
479 DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
480
481 /* "usbotg_fck" is an additional clock and not really a modulemode */
482 DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
483 AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
484 0x0, NULL);
485
486 DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
487 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
488 AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
489
490 /* Timers */
491 static const struct clksel timer1_clkmux_sel[] = {
492 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
493 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
494 { .parent = &tclkin_ck, .rates = div_1_2_rates },
495 { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
496 { .parent = &clk_32768_ck, .rates = div_1_4_rates },
497 { .parent = NULL },
498 };
499
500 static const char *timer1_ck_parents[] = {
501 "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
502 "clk_32768_ck",
503 };
504
505 static struct clk timer1_fck;
506
507 static const struct clk_ops timer1_fck_ops = {
508 .recalc_rate = &omap2_clksel_recalc,
509 .get_parent = &omap2_clksel_find_parent_index,
510 .set_parent = &omap2_clksel_set_parent,
511 .init = &omap2_init_clk_clkdm,
512 };
513
514 static struct clk_hw_omap timer1_fck_hw = {
515 .hw = {
516 .clk = &timer1_fck,
517 },
518 .clkdm_name = "l4ls_clkdm",
519 .clksel = timer1_clkmux_sel,
520 .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
521 .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
522 };
523
524 DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
525
526 static const struct clksel timer2_to_7_clk_sel[] = {
527 { .parent = &tclkin_ck, .rates = div_1_0_rates },
528 { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
529 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
530 { .parent = NULL },
531 };
532
533 static const char *timer2_to_7_ck_parents[] = {
534 "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
535 };
536
537 static struct clk timer2_fck;
538
539 static struct clk_hw_omap timer2_fck_hw = {
540 .hw = {
541 .clk = &timer2_fck,
542 },
543 .clkdm_name = "l4ls_clkdm",
544 .clksel = timer2_to_7_clk_sel,
545 .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
546 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
547 };
548
549 DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
550
551 static struct clk timer3_fck;
552
553 static struct clk_hw_omap timer3_fck_hw = {
554 .hw = {
555 .clk = &timer3_fck,
556 },
557 .clkdm_name = "l4ls_clkdm",
558 .clksel = timer2_to_7_clk_sel,
559 .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
560 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
561 };
562
563 DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
564
565 static struct clk timer4_fck;
566
567 static struct clk_hw_omap timer4_fck_hw = {
568 .hw = {
569 .clk = &timer4_fck,
570 },
571 .clkdm_name = "l4ls_clkdm",
572 .clksel = timer2_to_7_clk_sel,
573 .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
574 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
575 };
576
577 DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
578
579 static struct clk timer5_fck;
580
581 static struct clk_hw_omap timer5_fck_hw = {
582 .hw = {
583 .clk = &timer5_fck,
584 },
585 .clkdm_name = "l4ls_clkdm",
586 .clksel = timer2_to_7_clk_sel,
587 .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
588 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
589 };
590
591 DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
592
593 static struct clk timer6_fck;
594
595 static struct clk_hw_omap timer6_fck_hw = {
596 .hw = {
597 .clk = &timer6_fck,
598 },
599 .clkdm_name = "l4ls_clkdm",
600 .clksel = timer2_to_7_clk_sel,
601 .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
602 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
603 };
604
605 DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
606
607 static struct clk timer7_fck;
608
609 static struct clk_hw_omap timer7_fck_hw = {
610 .hw = {
611 .clk = &timer7_fck,
612 },
613 .clkdm_name = "l4ls_clkdm",
614 .clksel = timer2_to_7_clk_sel,
615 .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
616 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
617 };
618
619 DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
620
621 DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
622 "dpll_core_m5_ck",
623 &dpll_core_m5_ck,
624 0x0,
625 1, 2);
626
627 static const struct clk_ops cpsw_fck_ops = {
628 .recalc_rate = &omap2_clksel_recalc,
629 .get_parent = &omap2_clksel_find_parent_index,
630 .set_parent = &omap2_clksel_set_parent,
631 };
632
633 static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
634 { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
635 { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
636 { .parent = NULL },
637 };
638
639 static const char *cpsw_cpts_rft_ck_parents[] = {
640 "dpll_core_m5_ck", "dpll_core_m4_ck",
641 };
642
643 static struct clk cpsw_cpts_rft_clk;
644
645 static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
646 .hw = {
647 .clk = &cpsw_cpts_rft_clk,
648 },
649 .clkdm_name = "cpsw_125mhz_clkdm",
650 .clksel = cpsw_cpts_rft_clkmux_sel,
651 .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
652 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
653 };
654
655 DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
656
657
658 /* gpio */
659 static const char *gpio0_ck_parents[] = {
660 "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
661 };
662
663 static const struct clksel gpio0_dbclk_mux_sel[] = {
664 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
665 { .parent = &clk_32768_ck, .rates = div_1_1_rates },
666 { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
667 { .parent = NULL },
668 };
669
670 static const struct clk_ops gpio_fck_ops = {
671 .recalc_rate = &omap2_clksel_recalc,
672 .get_parent = &omap2_clksel_find_parent_index,
673 .set_parent = &omap2_clksel_set_parent,
674 .init = &omap2_init_clk_clkdm,
675 };
676
677 static struct clk gpio0_dbclk_mux_ck;
678
679 static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
680 .hw = {
681 .clk = &gpio0_dbclk_mux_ck,
682 },
683 .clkdm_name = "l4_wkup_clkdm",
684 .clksel = gpio0_dbclk_mux_sel,
685 .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
686 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
687 };
688
689 DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
690
691 DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
692 AM33XX_CM_WKUP_GPIO0_CLKCTRL,
693 AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
694
695 DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
696 AM33XX_CM_PER_GPIO1_CLKCTRL,
697 AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
698
699 DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
700 AM33XX_CM_PER_GPIO2_CLKCTRL,
701 AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
702
703 DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
704 AM33XX_CM_PER_GPIO3_CLKCTRL,
705 AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
706
707
708 static const char *pruss_ck_parents[] = {
709 "l3_gclk", "dpll_disp_m2_ck",
710 };
711
712 static const struct clksel pruss_ocp_clk_mux_sel[] = {
713 { .parent = &l3_gclk, .rates = div_1_0_rates },
714 { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
715 { .parent = NULL },
716 };
717
718 static struct clk pruss_ocp_gclk;
719
720 static struct clk_hw_omap pruss_ocp_gclk_hw = {
721 .hw = {
722 .clk = &pruss_ocp_gclk,
723 },
724 .clkdm_name = "pruss_ocp_clkdm",
725 .clksel = pruss_ocp_clk_mux_sel,
726 .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
727 .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
728 };
729
730 DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
731
732 static const char *lcd_ck_parents[] = {
733 "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
734 };
735
736 static const struct clksel lcd_clk_mux_sel[] = {
737 { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
738 { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
739 { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
740 { .parent = NULL },
741 };
742
743 static struct clk lcd_gclk;
744
745 static struct clk_hw_omap lcd_gclk_hw = {
746 .hw = {
747 .clk = &lcd_gclk,
748 },
749 .clkdm_name = "lcdc_clkdm",
750 .clksel = lcd_clk_mux_sel,
751 .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
752 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
753 };
754
755 DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
756 gpio_fck_ops, CLK_SET_RATE_PARENT);
757
758 DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
759
760 static const char *gfx_ck_parents[] = {
761 "dpll_core_m4_ck", "dpll_per_m2_ck",
762 };
763
764 static const struct clksel gfx_clksel_sel[] = {
765 { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
766 { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
767 { .parent = NULL },
768 };
769
770 static struct clk gfx_fclk_clksel_ck;
771
772 static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
773 .hw = {
774 .clk = &gfx_fclk_clksel_ck,
775 },
776 .clksel = gfx_clksel_sel,
777 .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
778 .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
779 };
780
781 DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
782
783 static const struct clk_div_table div_1_0_2_1_rates[] = {
784 { .div = 1, .val = 0, },
785 { .div = 2, .val = 1, },
786 { .div = 0 },
787 };
788
789 DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
790 &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
791 AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
792 0x0, div_1_0_2_1_rates, NULL);
793
794 static const char *sysclkout_ck_parents[] = {
795 "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
796 "lcd_gclk",
797 };
798
799 static const struct clksel sysclkout_pre_sel[] = {
800 { .parent = &clk_32768_ck, .rates = div_1_0_rates },
801 { .parent = &l3_gclk, .rates = div_1_1_rates },
802 { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
803 { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
804 { .parent = &lcd_gclk, .rates = div_1_4_rates },
805 { .parent = NULL },
806 };
807
808 static struct clk sysclkout_pre_ck;
809
810 static struct clk_hw_omap sysclkout_pre_ck_hw = {
811 .hw = {
812 .clk = &sysclkout_pre_ck,
813 },
814 .clksel = sysclkout_pre_sel,
815 .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
816 .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
817 };
818
819 DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
820
821 /* Divide by 8 clock rates with default clock is 1/1*/
822 static const struct clk_div_table div8_rates[] = {
823 { .div = 1, .val = 0, },
824 { .div = 2, .val = 1, },
825 { .div = 3, .val = 2, },
826 { .div = 4, .val = 3, },
827 { .div = 5, .val = 4, },
828 { .div = 6, .val = 5, },
829 { .div = 7, .val = 6, },
830 { .div = 8, .val = 7, },
831 { .div = 0 },
832 };
833
834 DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
835 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
836 AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
837
838 DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
839 AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
840
841 static const char *wdt_ck_parents[] = {
842 "clk_rc32k_ck", "clkdiv32k_ick",
843 };
844
845 static const struct clksel wdt_clkmux_sel[] = {
846 { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
847 { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
848 { .parent = NULL },
849 };
850
851 static struct clk wdt1_fck;
852
853 static struct clk_hw_omap wdt1_fck_hw = {
854 .hw = {
855 .clk = &wdt1_fck,
856 },
857 .clkdm_name = "l4_wkup_clkdm",
858 .clksel = wdt_clkmux_sel,
859 .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
860 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
861 };
862
863 DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
864
865 /*
866 * clkdev
867 */
868 static struct omap_clk am33xx_clks[] = {
869 CLK(NULL, "clk_32768_ck", &clk_32768_ck),
870 CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
871 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
872 CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
873 CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
874 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
875 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
876 CLK(NULL, "tclkin_ck", &tclkin_ck),
877 CLK(NULL, "dpll_core_ck", &dpll_core_ck),
878 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
879 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
880 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
881 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
882 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
883 CLK("cpu0", NULL, &dpll_mpu_ck),
884 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
885 CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
886 CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
887 CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
888 CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
889 CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
890 CLK(NULL, "dpll_per_ck", &dpll_per_ck),
891 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
892 CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
893 CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
894 CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
895 CLK(NULL, "cefuse_fck", &cefuse_fck),
896 CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
897 CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
898 CLK(NULL, "dcan0_fck", &dcan0_fck),
899 CLK("481cc000.d_can", NULL, &dcan0_fck),
900 CLK(NULL, "dcan1_fck", &dcan1_fck),
901 CLK("481d0000.d_can", NULL, &dcan1_fck),
902 CLK(NULL, "debugss_ick", &debugss_ick),
903 CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
904 CLK(NULL, "mcasp0_fck", &mcasp0_fck),
905 CLK(NULL, "mcasp1_fck", &mcasp1_fck),
906 CLK(NULL, "mmu_fck", &mmu_fck),
907 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
908 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
909 CLK(NULL, "sha0_fck", &sha0_fck),
910 CLK(NULL, "aes0_fck", &aes0_fck),
911 CLK(NULL, "timer1_fck", &timer1_fck),
912 CLK(NULL, "timer2_fck", &timer2_fck),
913 CLK(NULL, "timer3_fck", &timer3_fck),
914 CLK(NULL, "timer4_fck", &timer4_fck),
915 CLK(NULL, "timer5_fck", &timer5_fck),
916 CLK(NULL, "timer6_fck", &timer6_fck),
917 CLK(NULL, "timer7_fck", &timer7_fck),
918 CLK(NULL, "usbotg_fck", &usbotg_fck),
919 CLK(NULL, "ieee5000_fck", &ieee5000_fck),
920 CLK(NULL, "wdt1_fck", &wdt1_fck),
921 CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
922 CLK(NULL, "l3_gclk", &l3_gclk),
923 CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
924 CLK(NULL, "l4hs_gclk", &l4hs_gclk),
925 CLK(NULL, "l3s_gclk", &l3s_gclk),
926 CLK(NULL, "l4fw_gclk", &l4fw_gclk),
927 CLK(NULL, "l4ls_gclk", &l4ls_gclk),
928 CLK(NULL, "clk_24mhz", &clk_24mhz),
929 CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
930 CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
931 CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
932 CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
933 CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
934 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
935 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
936 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
937 CLK(NULL, "lcd_gclk", &lcd_gclk),
938 CLK(NULL, "mmc_clk", &mmc_clk),
939 CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
940 CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
941 CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
942 CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
943 CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
944 CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
945 };
946
947
948 static const char *enable_init_clks[] = {
949 "dpll_ddr_m2_ck",
950 "dpll_mpu_m2_ck",
951 "l3_gclk",
952 "l4hs_gclk",
953 "l4fw_gclk",
954 "l4ls_gclk",
955 };
956
am33xx_clk_init(void)957 int __init am33xx_clk_init(void)
958 {
959 if (soc_is_am33xx())
960 cpu_mask = RATE_IN_AM33XX;
961
962 omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
963
964 omap2_clk_disable_autoidle_all();
965
966 omap2_clk_enable_init_clocks(enable_init_clks,
967 ARRAY_SIZE(enable_init_clks));
968
969 /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
970 * physically present, in such a case HWMOD enabling of
971 * clock would be failure with default parent. And timer
972 * probe thinks clock is already enabled, this leads to
973 * crash upon accessing timer 3 & 6 registers in probe.
974 * Fix by setting parent of both these timers to master
975 * oscillator clock.
976 */
977
978 clk_set_parent(&timer3_fck, &sys_clkin_ck);
979 clk_set_parent(&timer6_fck, &sys_clkin_ck);
980 /*
981 * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
982 * the design/spec, so as a result, for example, timer which supposed
983 * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
984 * not expected by any use-case, so change WDT1 clock source to PRCM
985 * 32KHz clock.
986 */
987 clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
988
989 return 0;
990 }
991