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/arch/arm/mach-omap1/
Dams-delta-fiq-handler.S103 ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask
105 ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status
129 ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask
131 ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits
150 ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input
152 ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state
173 data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask
177 ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far,
190 ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask
/arch/m68k/ifpsp060/src/
Disp.S886 # (An) - fetch An value from stack #
887 # -(An) - fetch An value from stack; return decr value; #
891 # (An)+ - fetch An value from stack; return value; #
895 # (d16,An) - fetch An value from stack; read d16 using #
896 # _imem_read_word(); fetch may fail -> branch to #
898 # (xxx).w,(xxx).l - use _imem_read_{word,long}() to fetch #
899 # address; fetch may fail #
902 # (d16,PC) - fetch stacked PC value; read d16 using #
903 # _imem_read_word(); fetch may fail -> branch to #
917 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word
[all …]
Dpfpsp.S954 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr
1232 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1234 bsr.l _imem_read_long # fetch the instruction words
1322 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set
1327 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension
1439 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent
1531 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1843 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1850 mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr
1867 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
[all …]
Dfplsp.S577 bsr.l tag # fetch operand type
634 bsr.l tag # fetch operand type
693 bsr.l tag # fetch operand type
754 bsr.l tag # fetch operand type
811 bsr.l tag # fetch operand type
870 bsr.l tag # fetch operand type
931 bsr.l tag # fetch operand type
988 bsr.l tag # fetch operand type
1047 bsr.l tag # fetch operand type
1108 bsr.l tag # fetch operand type
[all …]
Dfpsp.S955 mov.l (tbl_unsupp.l,%pc,%d1.w*4),%d1 # fetch routine addr
1233 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1235 bsr.l _imem_read_long # fetch the instruction words
1323 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set
1328 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension
1440 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent
1532 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1844 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec
1851 mov.l (tbl_unsupp.l,%pc,%d1.l*4),%d1 # fetch routine addr
1868 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled
[all …]
Dilsp.S134 mov.l 0x8(%a6),%d7 # fetch divisor
/arch/ia64/lib/
Dclear_page.S45 .fetch: stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE label
47 br.cloop.sptk.few .fetch
/arch/alpha/lib/
Dev6-memcpy.S145 ldq $1, 0($17) # L : fetch 8
165 ldbu $1, 0($17) # L : fetch a byte
188 ldbu $1, 0($17) # L : fetch a byte
227 ldbu $1, 0($17) # L : fetch 1
Dev6-copy_user.S96 EXI( ldq_u $3,0($7) ) # .. L .. .. : Forward fetch for fallthrough code
/arch/m68k/ifpsp060/
Dos.S155 dmrbuae:movs.b (%a0),%d0 | fetch user byte
157 dmrbs: move.b (%a0),%d0 | fetch super byte
191 dmrwuae:movs.w (%a0), %d0 | fetch user word
193 dmrws: move.w (%a0), %d0 | fetch super word
226 dmrluae:movs.l (%a0),%d0 | fetch user longword
228 dmrls: move.l (%a0),%d0 | fetch super longword
/arch/unicore32/
DKconfig161 Unicore processors can not fetch/store information which is not
162 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
164 fetch/store instructions will be emulated in software if you say
/arch/unicore32/kernel/
Dhead.S177 nop @ fetch inst by phys addr
179 nop8 @ fetch inst by phys addr
/arch/sh/kernel/cpu/sh3/
Dswsusp.S116 stc r2_bank, k0 ! fetch old sp from r2_bank0
120 stc r0_bank, k3 ! fetch old pr from r0_bank0
/arch/arm/nwfpe/
Dentry.S85 ldr r1, [sp, #S_PSR] @ fetch the PSR
/arch/x86/include/asm/
Dkvm_emulate.h130 int (*fetch)(struct x86_emulate_ctxt *ctxt, member
313 struct fetch_cache fetch; member
/arch/arm/mach-omap2/
Dsram34xx.S259 ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
260 ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
/arch/sh/
DKconfig.cpu73 This enables support for a speculative instruction fetch for
/arch/x86/kvm/
Dtrace.h712 __entry->rip = vcpu->arch.emulate_ctxt.fetch.start;
715 - vcpu->arch.emulate_ctxt.fetch.start;
717 vcpu->arch.emulate_ctxt.fetch.data,
Dpaging_tmpl.h402 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, in FNAME() argument
633 r = FNAME(fetch)(vcpu, addr, &walker, write_fault, in FNAME()
Demulate.c789 unsigned size, bool write, bool fetch, in __linearize() argument
815 if (!fetch && (desc.type & 8) && !(desc.type & 2)) in __linearize()
846 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) in __linearize()
891 struct fetch_cache *fc = &ctxt->fetch; in do_insn_fetch_byte()
905 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size, in do_insn_fetch_byte()
4294 ctxt->fetch.start = ctxt->_eip; in x86_decode_insn()
4295 ctxt->fetch.end = ctxt->fetch.start + insn_len; in x86_decode_insn()
4297 memcpy(ctxt->fetch.data, insn, insn_len); in x86_decode_insn()
/arch/frv/
DKconfig169 write won't fetch a cacheline into the cache if there isn't already
/arch/powerpc/boot/dts/
Dvirtex440-ml507.dts105 xlnx,icu-rd-fetch-plb-prio = <0>;
Dvirtex440-ml510.dts100 xlnx,icu-rd-fetch-plb-prio = <0x0>;
/arch/sparc/lib/
Dchecksum_32.S137 addx %g0, %o2, %o2 ! fetch final carry
/arch/x86/math-emu/
DREADME134 The FPU instruction may be (usually will be) loaded into the pre-fetch

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