Searched refs:levels (Results 1 – 25 of 26) sorted by relevance
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| /arch/blackfin/mach-bf609/ |
| D | Kconfig | 55 int "SEC interrupt priority levels"
59 Divide the total number of interrupt priority levels into sub-levels.
60 There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
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| /arch/arm/boot/dts/ |
| D | wm8850-w70v2.dts | 22 brightness-levels = <0 40 60 80 100 130 190 255>;
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| D | tegra20-medcom-wide.dts | 37 brightness-levels = <0 4 8 16 32 64 128 255>;
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| D | imx28-tx28.dts | 113 brightness-levels = <0 4 8 16 32 64 128 255>;
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| D | imx23-evk.dts | 137 brightness-levels = <0 4 8 16 32 64 128 255>;
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| D | imx28-apf28dev.dts | 176 brightness-levels = <0 4 8 16 32 64 128 255>;
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| D | imx28-evk.dts | 347 brightness-levels = <0 4 8 16 32 64 128 255>;
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| D | imx28-cfa10049.dts | 344 brightness-levels = <0 4 8 16 32 64 128 255>;
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| D | omap4-sdp.dts | 101 brightness-levels = <
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| /arch/frv/kernel/ |
| D | irq.c | 152 #error dont know external IRQ trigger levels for this setup in init_IRQ()
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| /arch/ia64/kernel/ |
| D | topology.c | 312 unsigned long i, levels, unique_caches; in cpu_cache_sysfs_init() local
319 if ((status = ia64_pal_cache_summary(&levels, &unique_caches)) != 0) { in cpu_cache_sysfs_init()
329 for (i=0; i < levels; i++) { in cpu_cache_sysfs_init()
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| D | palinfo.c | 213 unsigned long i, levels, unique_caches; in cache_info() local
218 if ((status = ia64_pal_cache_summary(&levels, &unique_caches)) != 0) { in cache_info()
224 levels, unique_caches); in cache_info()
226 for (i=0; i < levels; i++) { in cache_info()
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| D | setup.c | 857 unsigned long l, levels, unique_caches; in get_cache_info() local
861 status = ia64_pal_cache_summary(&levels, &unique_caches); in get_cache_info()
873 for (l = 0; l < levels; ++l) { in get_cache_info()
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| /arch/sparc/kernel/ |
| D | sun4d_smp.c | 228 #define IGEN_MESSAGE(bcast, devid, sid, levels) \ argument
229 (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
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| /arch/ia64/pci/ |
| D | pci.c | 688 unsigned long levels, unique_caches; in set_pci_dfl_cacheline_size() local
692 status = ia64_pal_cache_summary(&levels, &unique_caches); in set_pci_dfl_cacheline_size()
699 status = ia64_pal_cache_config_info(levels - 1, in set_pci_dfl_cacheline_size()
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| /arch/powerpc/boot/dts/ |
| D | tqm5200.dts | 59 // 5200 interrupts are encoded into two levels;
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| D | charon.dts | 62 // 5200 interrupts are encoded into two levels;
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| D | lite5200.dts | 59 // 5200 interrupts are encoded into two levels;
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| D | mpc5200b.dtsi | 60 // 5200 interrupts are encoded into two levels;
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| /arch/x86/kernel/cpu/ |
| D | intel_cacheinfo.c | 220 static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 }; variable
280 eax->split.level = levels[leaf]; in amd_cpuid4()
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| /arch/arc/kernel/ |
| D | entry.S | 693 ; However with 2 levels of IRQ this can also happen even if
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| /arch/arm/mm/ |
| D | cache-v7.S | 107 b flush_levels @ start flushing cache levels
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| /arch/blackfin/ |
| D | Kconfig.debug | 151 The trace buffer does not record loops two levels deep. Helpful if
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| /arch/arm64/ |
| D | Kconfig | 176 allowing only two levels of page tables and faster TLB
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| /arch/mn10300/ |
| D | Kconfig | 433 what it does is restrict the levels of interrupt which are permitted
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