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Searched refs:mode0 (Results 1 – 5 of 5) sorted by relevance

/arch/mips/cavium-octeon/executive/
Dcvmx-helper-util.c306 pko_mode.s.mode0 = 4; in __cvmx_helper_setup_gmx()
308 pko_mode.s.mode0 = 3; in __cvmx_helper_setup_gmx()
310 pko_mode.s.mode0 = 2; in __cvmx_helper_setup_gmx()
312 pko_mode.s.mode0 = 1; in __cvmx_helper_setup_gmx()
314 pko_mode.s.mode0 = 0; in __cvmx_helper_setup_gmx()
/arch/arm/mach-omap2/
Dmux2420.h12 #define OMAP2420_MUX(mode0, mux_value) \ argument
14 .reg_offset = (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET), \
Dmux2430.h12 #define OMAP2430_MUX(mode0, mux_value) \ argument
14 .reg_offset = (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET), \
Dmux34xx.h12 #define OMAP3_MUX(mode0, mux_value) \ argument
14 .reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
/arch/mips/include/asm/octeon/
Dcvmx-pko-defs.h2447 uint64_t mode0:3; member
2449 uint64_t mode0:3;