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Searched refs:mult_div1_reg (Results 1 – 9 of 9) sorted by relevance

/arch/arm/mach-omap2/
Dcclock33xx_data.c81 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
158 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
205 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
255 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
294 .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
Dclkt2xxx_dpllcore.c144 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); in omap2_reprogram_dpllcore()
Ddpll3xxx.c321 v = __raw_readl(dd->mult_div1_reg); in omap3_noncore_dpll_program()
339 __raw_writel(v, dd->mult_div1_reg); in omap3_noncore_dpll_program()
Dclkt_dpll.c265 v = __raw_readl(dd->mult_div1_reg); in omap2_get_dpll_rate()
Dcclock44xx_data.c134 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
238 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
376 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
442 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
494 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
590 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
Dclock.h227 void __iomem *mult_div1_reg; member
Dcclock3xxx_data.c90 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
230 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
316 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
338 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
770 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
917 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
Dcclock2420_data.c96 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
Dcclock2430_data.c96 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),