1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999,2001-2006 Silicon Graphics, Inc. All rights reserved.
7 */
8
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/delay.h>
12 #include <linux/kernel.h>
13 #include <linux/kdev_t.h>
14 #include <linux/string.h>
15 #include <linux/screen_info.h>
16 #include <linux/console.h>
17 #include <linux/timex.h>
18 #include <linux/sched.h>
19 #include <linux/ioport.h>
20 #include <linux/mm.h>
21 #include <linux/serial.h>
22 #include <linux/irq.h>
23 #include <linux/bootmem.h>
24 #include <linux/mmzone.h>
25 #include <linux/interrupt.h>
26 #include <linux/acpi.h>
27 #include <linux/compiler.h>
28 #include <linux/root_dev.h>
29 #include <linux/nodemask.h>
30 #include <linux/pm.h>
31 #include <linux/efi.h>
32
33 #include <asm/io.h>
34 #include <asm/sal.h>
35 #include <asm/machvec.h>
36 #include <asm/processor.h>
37 #include <asm/vga.h>
38 #include <asm/setup.h>
39 #include <asm/sn/arch.h>
40 #include <asm/sn/addrs.h>
41 #include <asm/sn/pda.h>
42 #include <asm/sn/nodepda.h>
43 #include <asm/sn/sn_cpuid.h>
44 #include <asm/sn/simulator.h>
45 #include <asm/sn/leds.h>
46 #include <asm/sn/bte.h>
47 #include <asm/sn/shub_mmr.h>
48 #include <asm/sn/clksupport.h>
49 #include <asm/sn/sn_sal.h>
50 #include <asm/sn/geo.h>
51 #include <asm/sn/sn_feature_sets.h>
52 #include "xtalk/xwidgetdev.h"
53 #include "xtalk/hubdev.h"
54 #include <asm/sn/klconfig.h>
55
56
57 DEFINE_PER_CPU(struct pda_s, pda_percpu);
58
59 #define MAX_PHYS_MEMORY (1UL << IA64_MAX_PHYS_BITS) /* Max physical address supported */
60
61 extern void bte_init_node(nodepda_t *, cnodeid_t);
62
63 extern void sn_timer_init(void);
64 extern unsigned long last_time_offset;
65 extern void (*ia64_mark_idle) (int);
66 extern void snidle(int);
67
68 unsigned long sn_rtc_cycles_per_second;
69 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
70
71 DEFINE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
72 EXPORT_PER_CPU_SYMBOL(__sn_hub_info);
73
74 DEFINE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
75 EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid);
76
77 DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda);
78 EXPORT_PER_CPU_SYMBOL(__sn_nodepda);
79
80 char sn_system_serial_number_string[128];
81 EXPORT_SYMBOL(sn_system_serial_number_string);
82 u64 sn_partition_serial_number;
83 EXPORT_SYMBOL(sn_partition_serial_number);
84 u8 sn_partition_id;
85 EXPORT_SYMBOL(sn_partition_id);
86 u8 sn_system_size;
87 EXPORT_SYMBOL(sn_system_size);
88 u8 sn_sharing_domain_size;
89 EXPORT_SYMBOL(sn_sharing_domain_size);
90 u8 sn_coherency_id;
91 EXPORT_SYMBOL(sn_coherency_id);
92 u8 sn_region_size;
93 EXPORT_SYMBOL(sn_region_size);
94 int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
95
96 short physical_node_map[MAX_NUMALINK_NODES];
97 static unsigned long sn_prom_features[MAX_PROM_FEATURE_SETS];
98
99 EXPORT_SYMBOL(physical_node_map);
100
101 int num_cnodes;
102
103 static void sn_init_pdas(char **);
104 static void build_cnode_tables(void);
105
106 static nodepda_t *nodepdaindr[MAX_COMPACT_NODES];
107
108 /*
109 * The format of "screen_info" is strange, and due to early i386-setup
110 * code. This is just enough to make the console code think we're on a
111 * VGA color display.
112 */
113 struct screen_info sn_screen_info = {
114 .orig_x = 0,
115 .orig_y = 0,
116 .orig_video_mode = 3,
117 .orig_video_cols = 80,
118 .orig_video_ega_bx = 3,
119 .orig_video_lines = 25,
120 .orig_video_isVGA = 1,
121 .orig_video_points = 16
122 };
123
124 /*
125 * This routine can only be used during init, since
126 * smp_boot_data is an init data structure.
127 * We have to use smp_boot_data.cpu_phys_id to find
128 * the physical id of the processor because the normal
129 * cpu_physical_id() relies on data structures that
130 * may not be initialized yet.
131 */
132
pxm_to_nasid(int pxm)133 static int __init pxm_to_nasid(int pxm)
134 {
135 int i;
136 int nid;
137
138 nid = pxm_to_node(pxm);
139 for (i = 0; i < num_node_memblks; i++) {
140 if (node_memblk[i].nid == nid) {
141 return NASID_GET(node_memblk[i].start_paddr);
142 }
143 }
144 return -1;
145 }
146
147 /**
148 * early_sn_setup - early setup routine for SN platforms
149 *
150 * Sets up an initial console to aid debugging. Intended primarily
151 * for bringup. See start_kernel() in init/main.c.
152 */
153
early_sn_setup(void)154 void __init early_sn_setup(void)
155 {
156 efi_system_table_t *efi_systab;
157 efi_config_table_t *config_tables;
158 struct ia64_sal_systab *sal_systab;
159 struct ia64_sal_desc_entry_point *ep;
160 char *p;
161 int i, j;
162
163 /*
164 * Parse enough of the SAL tables to locate the SAL entry point. Since, console
165 * IO on SN2 is done via SAL calls, early_printk won't work without this.
166 *
167 * This code duplicates some of the ACPI table parsing that is in efi.c & sal.c.
168 * Any changes to those file may have to be made here as well.
169 */
170 efi_systab = (efi_system_table_t *) __va(ia64_boot_param->efi_systab);
171 config_tables = __va(efi_systab->tables);
172 for (i = 0; i < efi_systab->nr_tables; i++) {
173 if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) ==
174 0) {
175 sal_systab = __va(config_tables[i].table);
176 p = (char *)(sal_systab + 1);
177 for (j = 0; j < sal_systab->entry_count; j++) {
178 if (*p == SAL_DESC_ENTRY_POINT) {
179 ep = (struct ia64_sal_desc_entry_point
180 *)p;
181 ia64_sal_handler_init(__va
182 (ep->sal_proc),
183 __va(ep->gp));
184 return;
185 }
186 p += SAL_DESC_SIZE(*p);
187 }
188 }
189 }
190 /* Uh-oh, SAL not available?? */
191 printk(KERN_ERR "failed to find SAL entry point\n");
192 }
193
194 extern int platform_intr_list[];
195 static int __cpuinitdata shub_1_1_found;
196
197 /*
198 * sn_check_for_wars
199 *
200 * Set flag for enabling shub specific wars
201 */
202
is_shub_1_1(int nasid)203 static inline int __cpuinit is_shub_1_1(int nasid)
204 {
205 unsigned long id;
206 int rev;
207
208 if (is_shub2())
209 return 0;
210 id = REMOTE_HUB_L(nasid, SH1_SHUB_ID);
211 rev = (id & SH1_SHUB_ID_REVISION_MASK) >> SH1_SHUB_ID_REVISION_SHFT;
212 return rev <= 2;
213 }
214
sn_check_for_wars(void)215 static void __cpuinit sn_check_for_wars(void)
216 {
217 int cnode;
218
219 if (is_shub2()) {
220 /* none yet */
221 } else {
222 for_each_online_node(cnode) {
223 if (is_shub_1_1(cnodeid_to_nasid(cnode)))
224 shub_1_1_found = 1;
225 }
226 }
227 }
228
229 /*
230 * Scan the EFI PCDP table (if it exists) for an acceptable VGA console
231 * output device. If one exists, pick it and set sn_legacy_{io,mem} to
232 * reflect the bus offsets needed to address it.
233 *
234 * Since pcdp support in SN is not supported in the 2.4 kernel (or at least
235 * the one lbs is based on) just declare the needed structs here.
236 *
237 * Reference spec http://www.dig64.org/specifications/DIG64_PCDPv20.pdf
238 *
239 * Returns 0 if no acceptable vga is found, !0 otherwise.
240 *
241 * Note: This stuff is duped here because Altix requires the PCDP to
242 * locate a usable VGA device due to lack of proper ACPI support. Structures
243 * could be used from drivers/firmware/pcdp.h, but it was decided that moving
244 * this file to a more public location just for Altix use was undesirable.
245 */
246
247 struct hcdp_uart_desc {
248 u8 pad[45];
249 };
250
251 struct pcdp {
252 u8 signature[4]; /* should be 'HCDP' */
253 u32 length;
254 u8 rev; /* should be >=3 for pcdp, <3 for hcdp */
255 u8 sum;
256 u8 oem_id[6];
257 u64 oem_tableid;
258 u32 oem_rev;
259 u32 creator_id;
260 u32 creator_rev;
261 u32 num_type0;
262 struct hcdp_uart_desc uart[0]; /* num_type0 of these */
263 /* pcdp descriptors follow */
264 } __attribute__((packed));
265
266 struct pcdp_device_desc {
267 u8 type;
268 u8 primary;
269 u16 length;
270 u16 index;
271 /* interconnect specific structure follows */
272 /* device specific structure follows that */
273 } __attribute__((packed));
274
275 struct pcdp_interface_pci {
276 u8 type; /* 1 == pci */
277 u8 reserved;
278 u16 length;
279 u8 segment;
280 u8 bus;
281 u8 dev;
282 u8 fun;
283 u16 devid;
284 u16 vendid;
285 u32 acpi_interrupt;
286 u64 mmio_tra;
287 u64 ioport_tra;
288 u8 flags;
289 u8 translation;
290 } __attribute__((packed));
291
292 struct pcdp_vga_device {
293 u8 num_eas_desc;
294 /* ACPI Extended Address Space Desc follows */
295 } __attribute__((packed));
296
297 /* from pcdp_device_desc.primary */
298 #define PCDP_PRIMARY_CONSOLE 0x01
299
300 /* from pcdp_device_desc.type */
301 #define PCDP_CONSOLE_INOUT 0x0
302 #define PCDP_CONSOLE_DEBUG 0x1
303 #define PCDP_CONSOLE_OUT 0x2
304 #define PCDP_CONSOLE_IN 0x3
305 #define PCDP_CONSOLE_TYPE_VGA 0x8
306
307 #define PCDP_CONSOLE_VGA (PCDP_CONSOLE_TYPE_VGA | PCDP_CONSOLE_OUT)
308
309 /* from pcdp_interface_pci.type */
310 #define PCDP_IF_PCI 1
311
312 /* from pcdp_interface_pci.translation */
313 #define PCDP_PCI_TRANS_IOPORT 0x02
314 #define PCDP_PCI_TRANS_MMIO 0x01
315
316 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
317 static void
sn_scan_pcdp(void)318 sn_scan_pcdp(void)
319 {
320 u8 *bp;
321 struct pcdp *pcdp;
322 struct pcdp_device_desc device;
323 struct pcdp_interface_pci if_pci;
324 extern struct efi efi;
325
326 if (efi.hcdp == EFI_INVALID_TABLE_ADDR)
327 return; /* no hcdp/pcdp table */
328
329 pcdp = __va(efi.hcdp);
330
331 if (pcdp->rev < 3)
332 return; /* only support PCDP (rev >= 3) */
333
334 for (bp = (u8 *)&pcdp->uart[pcdp->num_type0];
335 bp < (u8 *)pcdp + pcdp->length;
336 bp += device.length) {
337 memcpy(&device, bp, sizeof(device));
338 if (! (device.primary & PCDP_PRIMARY_CONSOLE))
339 continue; /* not primary console */
340
341 if (device.type != PCDP_CONSOLE_VGA)
342 continue; /* not VGA descriptor */
343
344 memcpy(&if_pci, bp+sizeof(device), sizeof(if_pci));
345 if (if_pci.type != PCDP_IF_PCI)
346 continue; /* not PCI interconnect */
347
348 if (if_pci.translation & PCDP_PCI_TRANS_IOPORT)
349 vga_console_iobase = if_pci.ioport_tra;
350
351 if (if_pci.translation & PCDP_PCI_TRANS_MMIO)
352 vga_console_membase =
353 if_pci.mmio_tra | __IA64_UNCACHED_OFFSET;
354
355 break; /* once we find the primary, we're done */
356 }
357 }
358 #endif
359
360 static unsigned long sn2_rtc_initial;
361
362 /**
363 * sn_setup - SN platform setup routine
364 * @cmdline_p: kernel command line
365 *
366 * Handles platform setup for SN machines. This includes determining
367 * the RTC frequency (via a SAL call), initializing secondary CPUs, and
368 * setting up per-node data areas. The console is also initialized here.
369 */
sn_setup(char ** cmdline_p)370 void __init sn_setup(char **cmdline_p)
371 {
372 long status, ticks_per_sec, drift;
373 u32 version = sn_sal_rev();
374 extern void sn_cpu_init(void);
375
376 sn2_rtc_initial = rtc_time();
377 ia64_sn_plat_set_error_handling_features(); // obsolete
378 ia64_sn_set_os_feature(OSF_MCA_SLV_TO_OS_INIT_SLV);
379 ia64_sn_set_os_feature(OSF_FEAT_LOG_SBES);
380 /*
381 * Note: The calls to notify the PROM of ACPI and PCI Segment
382 * support must be done prior to acpi_load_tables(), as
383 * an ACPI capable PROM will rebuild the DSDT as result
384 * of the call.
385 */
386 ia64_sn_set_os_feature(OSF_PCISEGMENT_ENABLE);
387 ia64_sn_set_os_feature(OSF_ACPI_ENABLE);
388
389 /* Load the new DSDT and SSDT tables into the global table list. */
390 acpi_table_init();
391
392 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
393 /*
394 * Handle SN vga console.
395 *
396 * SN systems do not have enough ACPI table information
397 * being passed from prom to identify VGA adapters and the legacy
398 * addresses to access them. Until that is done, SN systems rely
399 * on the PCDP table to identify the primary VGA console if one
400 * exists.
401 *
402 * However, kernel PCDP support is optional, and even if it is built
403 * into the kernel, it will not be used if the boot cmdline contains
404 * console= directives.
405 *
406 * So, to work around this mess, we duplicate some of the PCDP code
407 * here so that the primary VGA console (as defined by PCDP) will
408 * work on SN systems even if a different console (e.g. serial) is
409 * selected on the boot line (or CONFIG_EFI_PCDP is off).
410 */
411
412 if (! vga_console_membase)
413 sn_scan_pcdp();
414
415 /*
416 * Setup legacy IO space.
417 * vga_console_iobase maps to PCI IO Space address 0 on the
418 * bus containing the VGA console.
419 */
420 if (vga_console_iobase) {
421 io_space[0].mmio_base =
422 (unsigned long) ioremap(vga_console_iobase, 0);
423 io_space[0].sparse = 0;
424 }
425
426 if (vga_console_membase) {
427 /* usable vga ... make tty0 the preferred default console */
428 if (!strstr(*cmdline_p, "console="))
429 add_preferred_console("tty", 0, NULL);
430 } else {
431 printk(KERN_DEBUG "SGI: Disabling VGA console\n");
432 if (!strstr(*cmdline_p, "console="))
433 add_preferred_console("ttySG", 0, NULL);
434 #ifdef CONFIG_DUMMY_CONSOLE
435 conswitchp = &dummy_con;
436 #else
437 conswitchp = NULL;
438 #endif /* CONFIG_DUMMY_CONSOLE */
439 }
440 #endif /* def(CONFIG_VT) && def(CONFIG_VGA_CONSOLE) */
441
442 MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY;
443
444 /*
445 * Build the tables for managing cnodes.
446 */
447 build_cnode_tables();
448
449 status =
450 ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
451 &drift);
452 if (status != 0 || ticks_per_sec < 100000) {
453 printk(KERN_WARNING
454 "unable to determine platform RTC clock frequency, guessing.\n");
455 /* PROM gives wrong value for clock freq. so guess */
456 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
457 } else
458 sn_rtc_cycles_per_second = ticks_per_sec;
459
460 platform_intr_list[ACPI_INTERRUPT_CPEI] = IA64_CPE_VECTOR;
461
462 printk("SGI SAL version %x.%02x\n", version >> 8, version & 0x00FF);
463
464 /*
465 * we set the default root device to /dev/hda
466 * to make simulation easy
467 */
468 ROOT_DEV = Root_HDA1;
469
470 /*
471 * Create the PDAs and NODEPDAs for all the cpus.
472 */
473 sn_init_pdas(cmdline_p);
474
475 ia64_mark_idle = &snidle;
476
477 /*
478 * For the bootcpu, we do this here. All other cpus will make the
479 * call as part of cpu_init in slave cpu initialization.
480 */
481 sn_cpu_init();
482
483 #ifdef CONFIG_SMP
484 init_smp_config();
485 #endif
486 screen_info = sn_screen_info;
487
488 sn_timer_init();
489
490 /*
491 * set pm_power_off to a SAL call to allow
492 * sn machines to power off. The SAL call can be replaced
493 * by an ACPI interface call when ACPI is fully implemented
494 * for sn.
495 */
496 pm_power_off = ia64_sn_power_down;
497 current->thread.flags |= IA64_THREAD_MIGRATION;
498 }
499
500 /**
501 * sn_init_pdas - setup node data areas
502 *
503 * One time setup for Node Data Area. Called by sn_setup().
504 */
sn_init_pdas(char ** cmdline_p)505 static void __init sn_init_pdas(char **cmdline_p)
506 {
507 cnodeid_t cnode;
508
509 /*
510 * Allocate & initialize the nodepda for each node.
511 */
512 for_each_online_node(cnode) {
513 nodepdaindr[cnode] =
514 alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t));
515 memset(nodepdaindr[cnode]->phys_cpuid, -1,
516 sizeof(nodepdaindr[cnode]->phys_cpuid));
517 spin_lock_init(&nodepdaindr[cnode]->ptc_lock);
518 }
519
520 /*
521 * Allocate & initialize nodepda for TIOs. For now, put them on node 0.
522 */
523 for (cnode = num_online_nodes(); cnode < num_cnodes; cnode++)
524 nodepdaindr[cnode] =
525 alloc_bootmem_node(NODE_DATA(0), sizeof(nodepda_t));
526
527 /*
528 * Now copy the array of nodepda pointers to each nodepda.
529 */
530 for (cnode = 0; cnode < num_cnodes; cnode++)
531 memcpy(nodepdaindr[cnode]->pernode_pdaindr, nodepdaindr,
532 sizeof(nodepdaindr));
533
534 /*
535 * Set up IO related platform-dependent nodepda fields.
536 * The following routine actually sets up the hubinfo struct
537 * in nodepda.
538 */
539 for_each_online_node(cnode) {
540 bte_init_node(nodepdaindr[cnode], cnode);
541 }
542
543 /*
544 * Initialize the per node hubdev. This includes IO Nodes and
545 * headless/memless nodes.
546 */
547 for (cnode = 0; cnode < num_cnodes; cnode++) {
548 hubdev_init_node(nodepdaindr[cnode], cnode);
549 }
550 }
551
552 /**
553 * sn_cpu_init - initialize per-cpu data areas
554 * @cpuid: cpuid of the caller
555 *
556 * Called during cpu initialization on each cpu as it starts.
557 * Currently, initializes the per-cpu data area for SNIA.
558 * Also sets up a few fields in the nodepda. Also known as
559 * platform_cpu_init() by the ia64 machvec code.
560 */
sn_cpu_init(void)561 void __cpuinit sn_cpu_init(void)
562 {
563 int cpuid;
564 int cpuphyid;
565 int nasid;
566 int subnode;
567 int slice;
568 int cnode;
569 int i;
570 static int wars_have_been_checked, set_cpu0_number;
571
572 cpuid = smp_processor_id();
573 if (cpuid == 0 && IS_MEDUSA()) {
574 if (ia64_sn_is_fake_prom())
575 sn_prom_type = 2;
576 else
577 sn_prom_type = 1;
578 printk(KERN_INFO "Running on medusa with %s PROM\n",
579 (sn_prom_type == 1) ? "real" : "fake");
580 }
581
582 memset(pda, 0, sizeof(pda));
583 if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2,
584 &sn_hub_info->nasid_bitmask,
585 &sn_hub_info->nasid_shift,
586 &sn_system_size, &sn_sharing_domain_size,
587 &sn_partition_id, &sn_coherency_id,
588 &sn_region_size))
589 BUG();
590 sn_hub_info->as_shift = sn_hub_info->nasid_shift - 2;
591
592 /*
593 * Don't check status. The SAL call is not supported on all PROMs
594 * but a failure is harmless.
595 * Architecturally, cpu_init is always called twice on cpu 0. We
596 * should set cpu_number on cpu 0 once.
597 */
598 if (cpuid == 0) {
599 if (!set_cpu0_number) {
600 (void) ia64_sn_set_cpu_number(cpuid);
601 set_cpu0_number = 1;
602 }
603 } else
604 (void) ia64_sn_set_cpu_number(cpuid);
605
606 /*
607 * The boot cpu makes this call again after platform initialization is
608 * complete.
609 */
610 if (nodepdaindr[0] == NULL)
611 return;
612
613 for (i = 0; i < MAX_PROM_FEATURE_SETS; i++)
614 if (ia64_sn_get_prom_feature_set(i, &sn_prom_features[i]) != 0)
615 break;
616
617 cpuphyid = get_sapicid();
618
619 if (ia64_sn_get_sapic_info(cpuphyid, &nasid, &subnode, &slice))
620 BUG();
621
622 for (i=0; i < MAX_NUMNODES; i++) {
623 if (nodepdaindr[i]) {
624 nodepdaindr[i]->phys_cpuid[cpuid].nasid = nasid;
625 nodepdaindr[i]->phys_cpuid[cpuid].slice = slice;
626 nodepdaindr[i]->phys_cpuid[cpuid].subnode = subnode;
627 }
628 }
629
630 cnode = nasid_to_cnodeid(nasid);
631
632 sn_nodepda = nodepdaindr[cnode];
633
634 pda->led_address =
635 (typeof(pda->led_address)) (LED0 + (slice << LED_CPU_SHIFT));
636 pda->led_state = LED_ALWAYS_SET;
637 pda->hb_count = HZ / 2;
638 pda->hb_state = 0;
639 pda->idle_flag = 0;
640
641 if (cpuid != 0) {
642 /* copy cpu 0's sn_cnodeid_to_nasid table to this cpu's */
643 memcpy(sn_cnodeid_to_nasid,
644 (&per_cpu(__sn_cnodeid_to_nasid, 0)),
645 sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid)));
646 }
647
648 /*
649 * Check for WARs.
650 * Only needs to be done once, on BSP.
651 * Has to be done after loop above, because it uses this cpu's
652 * sn_cnodeid_to_nasid table which was just initialized if this
653 * isn't cpu 0.
654 * Has to be done before assignment below.
655 */
656 if (!wars_have_been_checked) {
657 sn_check_for_wars();
658 wars_have_been_checked = 1;
659 }
660 sn_hub_info->shub_1_1_found = shub_1_1_found;
661
662 /*
663 * Set up addresses of PIO/MEM write status registers.
664 */
665 {
666 u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0};
667 u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_2,
668 SH2_PIO_WRITE_STATUS_1, SH2_PIO_WRITE_STATUS_3};
669 u64 *pio;
670 pio = is_shub1() ? pio1 : pio2;
671 pda->pio_write_status_addr =
672 (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, pio[slice]);
673 pda->pio_write_status_val = is_shub1() ? SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK : 0;
674 }
675
676 /*
677 * WAR addresses for SHUB 1.x.
678 */
679 if (local_node_data->active_cpu_count++ == 0 && is_shub1()) {
680 int buddy_nasid;
681 buddy_nasid =
682 cnodeid_to_nasid(numa_node_id() ==
683 num_online_nodes() - 1 ? 0 : numa_node_id() + 1);
684 pda->pio_shub_war_cam_addr =
685 (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid,
686 SH1_PI_CAM_CONTROL);
687 }
688 }
689
690 /*
691 * Build tables for converting between NASIDs and cnodes.
692 */
board_needs_cnode(int type)693 static inline int __init board_needs_cnode(int type)
694 {
695 return (type == KLTYPE_SNIA || type == KLTYPE_TIO);
696 }
697
build_cnode_tables(void)698 void __init build_cnode_tables(void)
699 {
700 int nasid;
701 int node;
702 lboard_t *brd;
703
704 memset(physical_node_map, -1, sizeof(physical_node_map));
705 memset(sn_cnodeid_to_nasid, -1,
706 sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid)));
707
708 /*
709 * First populate the tables with C/M bricks. This ensures that
710 * cnode == node for all C & M bricks.
711 */
712 for_each_online_node(node) {
713 nasid = pxm_to_nasid(node_to_pxm(node));
714 sn_cnodeid_to_nasid[node] = nasid;
715 physical_node_map[nasid] = node;
716 }
717
718 /*
719 * num_cnodes is total number of C/M/TIO bricks. Because of the 256 node
720 * limit on the number of nodes, we can't use the generic node numbers
721 * for this. Note that num_cnodes is incremented below as TIOs or
722 * headless/memoryless nodes are discovered.
723 */
724 num_cnodes = num_online_nodes();
725
726 /* fakeprom does not support klgraph */
727 if (IS_RUNNING_ON_FAKE_PROM())
728 return;
729
730 /* Find TIOs & headless/memoryless nodes and add them to the tables */
731 for_each_online_node(node) {
732 kl_config_hdr_t *klgraph_header;
733 nasid = cnodeid_to_nasid(node);
734 klgraph_header = ia64_sn_get_klconfig_addr(nasid);
735 BUG_ON(klgraph_header == NULL);
736 brd = NODE_OFFSET_TO_LBOARD(nasid, klgraph_header->ch_board_info);
737 while (brd) {
738 if (board_needs_cnode(brd->brd_type) && physical_node_map[brd->brd_nasid] < 0) {
739 sn_cnodeid_to_nasid[num_cnodes] = brd->brd_nasid;
740 physical_node_map[brd->brd_nasid] = num_cnodes++;
741 }
742 brd = find_lboard_next(brd);
743 }
744 }
745 }
746
747 int
nasid_slice_to_cpuid(int nasid,int slice)748 nasid_slice_to_cpuid(int nasid, int slice)
749 {
750 long cpu;
751
752 for (cpu = 0; cpu < nr_cpu_ids; cpu++)
753 if (cpuid_to_nasid(cpu) == nasid &&
754 cpuid_to_slice(cpu) == slice)
755 return cpu;
756
757 return -1;
758 }
759
sn_prom_feature_available(int id)760 int sn_prom_feature_available(int id)
761 {
762 if (id >= BITS_PER_LONG * MAX_PROM_FEATURE_SETS)
763 return 0;
764 return test_bit(id, sn_prom_features);
765 }
766
767 void
sn_kernel_launch_event(void)768 sn_kernel_launch_event(void)
769 {
770 /* ignore status until we understand possible failure, if any*/
771 if (ia64_sn_kernel_launch_event())
772 printk(KERN_ERR "KEXEC is not supported in this PROM, Please update the PROM.\n");
773 }
774 EXPORT_SYMBOL(sn_prom_feature_available);
775
776