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Searched refs:out_8 (Results 1 – 25 of 56) sorted by relevance

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/arch/powerpc/platforms/embedded6xx/
Dls_uart.c40 out_8(avr_addr + UART_TX, string[i]); in wd_stop()
66 out_8(avr_addr + UART_LCR, cval); /* initialise UART */ in avr_uart_configure()
67 out_8(avr_addr + UART_MCR, 0); in avr_uart_configure()
68 out_8(avr_addr + UART_IER, 0); in avr_uart_configure()
72 out_8(avr_addr + UART_LCR, cval); /* Set character format */ in avr_uart_configure()
74 out_8(avr_addr + UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ in avr_uart_configure()
75 out_8(avr_addr + UART_DLL, quot & 0xff); /* LS of divisor */ in avr_uart_configure()
76 out_8(avr_addr + UART_DLM, quot >> 8); /* MS of divisor */ in avr_uart_configure()
77 out_8(avr_addr + UART_LCR, cval); /* reset DLAB */ in avr_uart_configure()
78 out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO); /* enable FIFO */ in avr_uart_configure()
[all …]
/arch/powerpc/boot/
Dvirtex.c58 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB); in virtex_ns16550_console_init()
61 out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF); in virtex_ns16550_console_init()
62 out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8); in virtex_ns16550_console_init()
65 out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8); in virtex_ns16550_console_init()
68 out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR); in virtex_ns16550_console_init()
71 out_8(reg_base + (UART_FCR << reg_shift), in virtex_ns16550_console_init()
Dns16550.c34 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
41 out_8(reg_base, c); in ns16550_putc()
Dmpc52xx-psc.c38 out_8(psc + MPC52xx_PSC_BUFFER, c); in psc_putc()
Dio.h20 static inline void out_8(volatile unsigned char *addr, int val) in out_8() function
/arch/powerpc/platforms/powermac/
Dnvram.c157 out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val); in direct_nvram_write_byte()
167 out_8(nvram_addr, addr >> 5); in indirect_nvram_read_byte()
179 out_8(nvram_addr, addr >> 5); in indirect_nvram_write_byte()
180 out_8(&nvram_data[(addr & 0x1f) << 4], val); in indirect_nvram_write_byte()
288 out_8(base, SM_FLASH_CMD_ERASE_SETUP); in sm_erase_bank()
289 out_8(base, SM_FLASH_CMD_ERASE_CONFIRM); in sm_erase_bank()
296 out_8(base, SM_FLASH_CMD_READ_STATUS); in sm_erase_bank()
300 out_8(base, SM_FLASH_CMD_CLEAR_STATUS); in sm_erase_bank()
301 out_8(base, SM_FLASH_CMD_RESET); in sm_erase_bank()
320 out_8(base+i, SM_FLASH_CMD_WRITE_SETUP); in sm_write_bank()
[all …]
Dudbg_scc.c32 out_8(sccd, c); in udbg_scc_putc()
124 out_8(sccc, 0x09); /* reset A or B side */ in udbg_scc_init()
125 out_8(sccc, 0xc0); in udbg_scc_init()
131 out_8(sccc, 13); in udbg_scc_init()
133 out_8(sccc, 12); in udbg_scc_init()
148 out_8(sccc, scc_inittab[i]); in udbg_scc_init()
Dtime.c283 out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT); in via_calibrate_decr()
285 out_8(&via[T1CH], 2); in via_calibrate_decr()
287 out_8(&via[T1LL], count); in via_calibrate_decr()
288 out_8(&via[T1LH], count >> 8); in via_calibrate_decr()
/arch/powerpc/kernel/
Dudbg_16550.c66 out_8(&udbg_comport->thr, c); in udbg_550_putc()
106 out_8(&udbg_comport->lcr, 0x00); in udbg_init_uart()
107 out_8(&udbg_comport->ier, 0xff); in udbg_init_uart()
108 out_8(&udbg_comport->ier, 0x00); in udbg_init_uart()
109 out_8(&udbg_comport->lcr, LCR_DLAB); in udbg_init_uart()
110 out_8(&udbg_comport->dll, dll & 0xff); in udbg_init_uart()
111 out_8(&udbg_comport->dlm, dll >> 8); in udbg_init_uart()
113 out_8(&udbg_comport->lcr, 0x03); in udbg_init_uart()
115 out_8(&udbg_comport->mcr, 0x03); in udbg_init_uart()
117 out_8(&udbg_comport->fcr ,0x07); in udbg_init_uart()
[all …]
/arch/powerpc/platforms/52xx/
Dmpc52xx_pm.c41 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
43 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); in mpc52xx_set_wakeup_gpio()
45 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); in mpc52xx_set_wakeup_gpio()
52 out_8(&gpiow->wkup_maste, 1); in mpc52xx_set_wakeup_gpio()
134 out_8(&cdm->ccs_sleep_enable, 1); in mpc52xx_pm_enter()
135 out_8(&cdm->osc_sleep_enable, 1); in mpc52xx_pm_enter()
136 out_8(&cdm->ccs_qreq_test, 1); in mpc52xx_pm_enter()
168 out_8(&cdm->ccs_sleep_enable, 0); in mpc52xx_pm_enter()
169 out_8(&cdm->osc_sleep_enable, 0); in mpc52xx_pm_enter()
Dlite5200_pm.c138 out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel); in lite5200_restore_regs()
139 out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel); in lite5200_restore_regs()
141 out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en); in lite5200_restore_regs()
142 out_8(&cdm->fd_enable, scdm.fd_enable); in lite5200_restore_regs()
147 out_8(&cdm->osc_disable, scdm.osc_disable); in lite5200_restore_regs()
161 out_8(&bes->IntVect1, sbes.IntVect1); in lite5200_restore_regs()
162 out_8(&bes->IntVect2, sbes.IntVect2); in lite5200_restore_regs()
166 out_8(&bes->ipr[i], sbes.ipr[i]); in lite5200_restore_regs()
Dlite5200.c72 out_8(&cdm->ext_48mhz_en, 0x00); in lite5200_fix_clock_config()
73 out_8(&cdm->fd_enable, 0x01); in lite5200_fix_clock_config()
Dmpc52xx_lpbfifo.c113 out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 7); in mpc52xx_lpbfifo_kick()
117 out_8(lpbfifo.regs + LPBFIFO_REG_FIFO_CONTROL, 0); in mpc52xx_lpbfifo_kick()
174 out_8(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, 0x01); in mpc52xx_lpbfifo_kick()
286 out_8(lpbfifo.regs + LPBFIFO_REG_BYTES_DONE_STATUS, 0x01); in mpc52xx_lpbfifo_irq()
449 out_8(lpbfifo.regs + LPBFIFO_REG_PACKET_SIZE, 0x01); in mpc52xx_lpbfifo_start_xfer()
/arch/m68k/hp300/
Dtime.c67 out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ in hp300_sched_init()
68 out_8(CLOCKBASE + CLKCR1, 0x1); /* reset */ in hp300_sched_init()
75 out_8(CLOCKBASE + CLKCR2, 0x1); /* select CR1 */ in hp300_sched_init()
76 out_8(CLOCKBASE + CLKCR1, 0x40); /* enable irq */ in hp300_sched_init()
/arch/powerpc/platforms/512x/
Dmpc5121_ads_cpld.c67 out_8(pic_mask, in cpld_mask_irq()
77 out_8(pic_mask, in cpld_unmask_irq()
186 out_8(&cpld_regs->route, 0xfd); in mpc5121_ads_cpld_pic_init()
187 out_8(&cpld_regs->pci_mask, 0xff); in mpc5121_ads_cpld_pic_init()
189 out_8(&cpld_regs->misc_mask, ~(MISC_IGNORE)); in mpc5121_ads_cpld_pic_init()
/arch/powerpc/platforms/40x/
Dep405.c90 out_8(bcsr_regs + BCSR_XIRQ_SELECT, i); in ep405_init_bcsr()
91 out_8(bcsr_regs + BCSR_XIRQ_ROUTING, irq); in ep405_init_bcsr()
95 out_8(bcsr_regs + BCSR_GPIO_IRQ_PAR_CTRL, 0xfe); in ep405_init_bcsr()
/arch/m68k/include/asm/
Dblinken.h28 out_8(HP300_LEDS, ~hp300_ledstate); in blinken_leds()
Draw_io.h43 #define out_8(addr,b) (void)((*(__force volatile u8 *) (addr)) = (b)) macro
56 #define raw_outb(val,port) out_8((port),(val))
59 #define __raw_writeb(val,addr) out_8((addr),(val))
128 out_8(port, *buf++); in raw_outsb()
Dq40_master.h43 #define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_)
Dio_mm.h127 #define writeb(v, addr) out_8((addr), (v))
246 #define isa_outb(val,port) out_8(isa_itb(port),(val))
254 #define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val))
394 #define outb(val, port) ((port) < 1024 ? isa_rom_outb((val), (port)) : out_8((port), (val)))
395 #define outb_p(val, port) ((port) < 1024 ? isa_rom_outb_p((val), (port)) : out_8((port), (val)))
409 #define writeb(val, addr) out_8((addr), (val))
442 #define writeb(val,addr) out_8((addr),(val))
Dide.h51 #define writeb(val, port) out_8(port, val)
/arch/powerpc/platforms/85xx/
Dp1022_ds.c313 out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */ in p1022ds_set_monitor_port()
316 out_8(lbc_lcs1_ba, b); in p1022ds_set_monitor_port()
328 out_8(lbc_lcs0_ba, PX_BRDCFG1); in p1022ds_set_monitor_port()
332 out_8(lbc_lcs1_ba, b); in p1022ds_set_monitor_port()
340 out_8(lbc_lcs0_ba, PX_BRDCFG1); in p1022ds_set_monitor_port()
344 out_8(lbc_lcs1_ba, b); in p1022ds_set_monitor_port()
/arch/powerpc/platforms/83xx/
Dmpc834x_mds.c67 out_8(bcsr_regs + 5, (bcsr5 | BCSR5_INT_USB)); in mpc834xemds_usb_cfg()
Dmpc837x_mds.c64 out_8(bcsr_regs + 12, bcsr12); in mpc837xmds_usb_cfg()
/arch/powerpc/sysdev/xics/
Dicp-native.c75 out_8(&icp_native_regs[cpu]->xirr.bytes[0], value); in icp_native_set_cppr()
80 out_8(&icp_native_regs[n_cpu]->qirr.bytes[0], value); in icp_native_set_qirr()

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