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Searched refs:prediv (Results 1 – 7 of 7) sorted by relevance

/arch/mips/ar7/
Dclock.c84 u32 prediv; member
111 static void approximate(int base, int target, int *prediv, in approximate() argument
122 *prediv = j; in approximate()
128 static void calculate(int base, int target, int *prediv, int *postdiv, in calculate() argument
133 for (*prediv = 1; *prediv <= 32; (*prediv)++) { in calculate()
134 tmp_base = base / *prediv; in calculate()
144 if (base / *prediv * *mul / *postdiv != target) { in calculate()
145 approximate(base, target, prediv, postdiv, mul); in calculate()
146 tmp_freq = base / *prediv * *mul / *postdiv; in calculate()
153 *prediv, *postdiv, *mul); in calculate()
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/arch/frv/kernel/
Dtime.c74 unsigned short base, pre, prediv; in time_divisor_init() local
78 prediv = 4; in time_divisor_init()
79 base = __res_bus_clock_speed_HZ / pre / HZ / (1 << prediv); in time_divisor_init()
82 __set_TxCKSL_DATA(0, prediv); in time_divisor_init()
/arch/arm/mach-davinci/
Dclock.c410 u32 ctrl, mult = 1, prediv = 1, postdiv = 1; in clk_pllclk_recalc() local
429 prediv = __raw_readl(pll->base + PREDIV); in clk_pllclk_recalc()
430 if (prediv & PLLDIV_EN) in clk_pllclk_recalc()
431 prediv = (prediv & pll->div_ratio_mask) + 1; in clk_pllclk_recalc()
433 prediv = 1; in clk_pllclk_recalc()
438 prediv = 8; in clk_pllclk_recalc()
449 rate /= prediv; in clk_pllclk_recalc()
458 if (prediv > 1) in clk_pllclk_recalc()
459 pr_debug("/ %d ", prediv); in clk_pllclk_recalc()
479 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, in davinci_set_pllrate() argument
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Dda850.c944 unsigned int prediv; member
953 .prediv = 1,
962 .prediv = 1,
971 .prediv = 2,
980 .prediv = 1,
989 .prediv = 1,
998 .prediv = 1,
1123 unsigned int prediv, mult, postdiv; in da850_set_pll0rate() local
1129 prediv = opp->prediv; in da850_set_pll0rate()
1133 ret = davinci_set_pllrate(pll, prediv, mult, postdiv); in da850_set_pll0rate()
Dclock.h128 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
Dtnetv107x.c650 unsigned long mult = 0, prediv = 1, postdiv = 1; in clk_sspll_recalc() local
676 prediv = __raw_readl(&sspll_regs[pll]->pre_div) + 1; in clk_sspll_recalc()
694 ret /= (prediv * postdiv); in clk_sspll_recalc()
/arch/c6x/platforms/
Dpll.c271 u32 ctrl, mult = 0, prediv = 0, postdiv = 0; in clk_pllclk_recalc() local
292 prediv = pll_read(pll, PLLPRE); in clk_pllclk_recalc()
293 if (prediv & PLLDIV_EN) in clk_pllclk_recalc()
294 prediv = (prediv & PLLDIV_RATIO_MASK) + 1; in clk_pllclk_recalc()
296 prediv = 0; in clk_pllclk_recalc()
307 if (prediv) in clk_pllclk_recalc()
308 rate /= prediv; in clk_pllclk_recalc()
317 prediv, mult, postdiv, rate / 1000000); in clk_pllclk_recalc()