1 /* 2 * Format of an instruction in memory. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 2000 by Ralf Baechle 9 * Copyright (C) 2006 by Thiemo Seufer 10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 11 */ 12 #ifndef _UAPI_ASM_INST_H 13 #define _UAPI_ASM_INST_H 14 15 /* 16 * Major opcodes; before MIPS IV cop1x was called cop3. 17 */ 18 enum major_op { 19 spec_op, bcond_op, j_op, jal_op, 20 beq_op, bne_op, blez_op, bgtz_op, 21 #ifndef CONFIG_CPU_MIPSR6 22 addi_op, addiu_op, slti_op, sltiu_op, 23 #else 24 cbcond0_op, addiu_op, slti_op, sltiu_op, 25 #endif 26 andi_op, ori_op, xori_op, lui_op, 27 cop0_op, cop1_op, cop2_op, cop1x_op, 28 beql_op, bnel_op, blezl_op, bgtzl_op, 29 #ifndef CONFIG_CPU_MIPSR6 30 daddi_op, daddiu_op, ldl_op, ldr_op, 31 #else 32 cbcond1_op, daddiu_op, ldl_op, ldr_op, 33 #endif 34 spec2_op, jalx_op, mdmx_op, spec3_op, 35 lb_op, lh_op, lwl_op, lw_op, 36 lbu_op, lhu_op, lwr_op, lwu_op, 37 sb_op, sh_op, swl_op, sw_op, 38 sdl_op, sdr_op, swr_op, cache_op, 39 #ifndef CONFIG_CPU_MIPSR6 40 ll_op, lwc1_op, lwc2_op, pref_op, 41 lld_op, ldc1_op, ldc2_op, ld_op, 42 sc_op, swc1_op, swc2_op, major_3b_op, 43 scd_op, sdc1_op, sdc2_op, sd_op 44 #else 45 ll_op, lwc1_op, bc_op, pref_op, 46 lld_op, ldc1_op, jump_op, ld_op, 47 sc_op, swc1_op, balc_op, pcrel_op, 48 scd_op, sdc1_op, jump2_op, sd_op 49 #endif 50 }; 51 #define msa_op mdmx_op 52 53 /* 54 * func field of spec opcode. 55 */ 56 enum spec_op { 57 sll_op, movc_op, srl_op, sra_op, 58 sllv_op, pmon_op, srlv_op, srav_op, 59 jr_op, jalr_op, movz_op, movn_op, 60 syscall_op, break_op, spim_op, sync_op, 61 mfhi_op, mthi_op, mflo_op, mtlo_op, 62 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, 63 mult_op, multu_op, div_op, divu_op, 64 dmult_op, dmultu_op, ddiv_op, ddivu_op, 65 add_op, addu_op, sub_op, subu_op, 66 and_op, or_op, xor_op, nor_op, 67 spec3_unused_op, spec4_unused_op, slt_op, sltu_op, 68 dadd_op, daddu_op, dsub_op, dsubu_op, 69 tge_op, tgeu_op, tlt_op, tltu_op, 70 teq_op, spec5_unused_op, tne_op, spec6_unused_op, 71 dsll_op, spec7_unused_op, dsrl_op, dsra_op, 72 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op 73 }; 74 75 /* 76 * func field of spec2 opcode. 77 */ 78 enum spec2_op { 79 madd_op, maddu_op, mul_op, spec2_3_unused_op, 80 msub_op, msubu_op, /* more unused ops */ 81 clz_op = 0x20, clo_op, 82 dclz_op = 0x24, dclo_op, 83 sdbpp_op = 0x3f 84 }; 85 86 /* 87 * func field of spec3 opcode. 88 */ 89 enum spec3_op { 90 ext_op, dextm_op, dextu_op, dext_op, 91 ins_op, dinsm_op, dinsu_op, dins_op, 92 lx_op = 0x0a, 93 lwle_op = 0x19, 94 lwre_op = 0x1a, cachee_op = 0x1b, 95 sbe_op = 0x1c, she_op = 0x1d, 96 sce_op = 0x1e, swe_op = 0x1f, 97 bshfl_op = 0x20, swle_op = 0x21, 98 swre_op = 0x22, prefe_op = 0x23, 99 dbshfl_op = 0x24, cache6_op = 0x25, 100 sc6_op = 0x26, scd6_op = 0x27, 101 lbue_op = 0x28, lhue_op = 0x29, 102 lbe_op = 0x2c, lhe_op = 0x2d, 103 lle_op = 0x2e, lwe_op = 0x2f, 104 pref6_op = 0x35, ll6_op = 0x36, 105 lld6_op = 0x37, 106 rdhwr_op = 0x3b 107 }; 108 109 /* 110 * rt field of bcond opcodes. 111 */ 112 enum rt_op { 113 bltz_op, bgez_op, bltzl_op, bgezl_op, 114 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, 115 tgei_op, tgeiu_op, tlti_op, tltiu_op, 116 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, 117 bltzal_op, bgezal_op, bltzall_op, bgezall_op, 118 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, 119 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, 120 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f 121 }; 122 123 /* 124 * rs field of cop opcodes. 125 */ 126 enum cop_op { 127 mfc_op = 0x00, dmfc_op = 0x01, 128 cfc_op = 0x02, mfhc_op = 0x03, 129 mtc_op = 0x04, dmtc_op = 0x05, 130 ctc_op = 0x06, mthc_op = 0x07, 131 rs_bc_op = 0x08, bc1eqz_op = 0x09, 132 bc1nez_op = 0x0d, cop_op = 0x10, 133 copm_op = 0x18 134 }; 135 136 /* 137 * rt field of cop.rs_bc_op opcodes 138 */ 139 enum bcop_op { 140 bcf_op, bct_op, bcfl_op, bctl_op 141 }; 142 143 /* 144 * func field of cop0 coi opcodes. 145 */ 146 enum cop0_coi_func { 147 tlbr_op = 0x01, tlbwi_op = 0x02, 148 tlbwr_op = 0x06, tlbp_op = 0x08, 149 rfe_op = 0x10, eret_op = 0x18 150 }; 151 152 /* 153 * func field of cop0 com opcodes. 154 */ 155 enum cop0_com_func { 156 tlbr1_op = 0x01, tlbw_op = 0x02, 157 tlbp1_op = 0x08, dctr_op = 0x09, 158 dctw_op = 0x0a 159 }; 160 161 /* 162 * fmt field of cop1 opcodes. 163 */ 164 enum cop1_fmt { 165 s_fmt, d_fmt, e_fmt, q_fmt, 166 w_fmt, l_fmt 167 }; 168 169 /* 170 * func field of cop1 instructions using d, s or w format. 171 */ 172 enum cop1_sdw_func { 173 fadd_op = 0x00, fsub_op = 0x01, 174 fmul_op = 0x02, fdiv_op = 0x03, 175 fsqrt_op = 0x04, fabs_op = 0x05, 176 fmov_op = 0x06, fneg_op = 0x07, 177 froundl_op = 0x08, ftruncl_op = 0x09, 178 fceill_op = 0x0a, ffloorl_op = 0x0b, 179 fround_op = 0x0c, ftrunc_op = 0x0d, 180 fceil_op = 0x0e, ffloor_op = 0x0f, 181 fsel_op = 0x10, 182 fmovc_op = 0x11, fmovz_op = 0x12, 183 fmovn_op = 0x13, fseleqz_op = 0x14, 184 frecip_op = 0x15, frsqrt_op = 0x16, 185 fselnez_op = 0x17, 186 fmaddf_op = 0x18, fmsubf_op = 0x19, 187 frint_op = 0x1a, fclass_op = 0x1b, 188 fmin_op = 0x1c, fmina_op = 0x1d, 189 fmax_op = 0x1e, fmaxa_op = 0x1f, 190 fcvts_op = 0x20, 191 fcvtd_op = 0x21, fcvte_op = 0x22, 192 fcvtw_op = 0x24, fcvtl_op = 0x25, 193 fcmp_op = 0x30 194 }; 195 196 /* 197 * func field of cop1x opcodes (MIPS IV). 198 */ 199 enum cop1x_func { 200 lwxc1_op = 0x00, ldxc1_op = 0x01, 201 swxc1_op = 0x08, sdxc1_op = 0x09, 202 pfetch_op = 0x0f, madd_s_op = 0x20, 203 madd_d_op = 0x21, madd_e_op = 0x22, 204 msub_s_op = 0x28, msub_d_op = 0x29, 205 msub_e_op = 0x2a, nmadd_s_op = 0x30, 206 nmadd_d_op = 0x31, nmadd_e_op = 0x32, 207 nmsub_s_op = 0x38, nmsub_d_op = 0x39, 208 nmsub_e_op = 0x3a 209 }; 210 211 /* 212 * func field for mad opcodes (MIPS IV). 213 */ 214 enum mad_func { 215 madd_fp_op = 0x08, msub_fp_op = 0x0a, 216 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e 217 }; 218 219 /* 220 * func field for special3 lx opcodes (Cavium Octeon). 221 */ 222 enum lx_func { 223 lwx_op = 0x00, 224 lhx_op = 0x04, 225 lbux_op = 0x06, 226 ldx_op = 0x08, 227 lwux_op = 0x10, 228 lhux_op = 0x14, 229 lbx_op = 0x16, 230 }; 231 232 /* 233 * func field for MSA MI10 format 234 */ 235 enum msa_mi10_func { 236 msa_ld_op = 8, 237 msa_st_op = 9, 238 }; 239 240 enum relpc_op { 241 addiupc_op = 0, 242 lwpc_op = 1, 243 lwupc_op = 2, 244 }; 245 246 enum relpc_func { 247 auipc_func = 6, 248 aluipc_func = 7, 249 }; 250 251 /* 252 * (microMIPS) Major opcodes. 253 */ 254 enum mm_major_op { 255 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, 256 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, 257 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, 258 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, 259 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, 260 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op, 261 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, 262 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, 263 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, 264 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, 265 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, 266 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, 267 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, 268 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, 269 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, 270 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, 271 }; 272 273 /* 274 * (microMIPS) POOL32I minor opcodes. 275 */ 276 enum mm_32i_minor_op { 277 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, 278 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, 279 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, 280 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, 281 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, 282 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, 283 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, 284 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, 285 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, 286 }; 287 288 /* 289 * (microMIPS) POOL32A minor opcodes. 290 */ 291 enum mm_32a_minor_op { 292 mm_sll32_op = 0x000, 293 mm_ins_op = 0x00c, 294 mm_ext_op = 0x02c, 295 mm_pool32axf_op = 0x03c, 296 mm_srl32_op = 0x040, 297 mm_sra_op = 0x080, 298 mm_rotr_op = 0x0c0, 299 mm_lwxs_op = 0x118, 300 mm_addu32_op = 0x150, 301 mm_subu32_op = 0x1d0, 302 mm_and_op = 0x250, 303 mm_or32_op = 0x290, 304 mm_xor32_op = 0x310, 305 }; 306 307 /* 308 * (microMIPS) POOL32B functions. 309 */ 310 enum mm_32b_func { 311 mm_lwc2_func = 0x0, 312 mm_lwp_func = 0x1, 313 mm_ldc2_func = 0x2, 314 mm_ldp_func = 0x4, 315 mm_lwm32_func = 0x5, 316 mm_cache_func = 0x6, 317 mm_ldm_func = 0x7, 318 mm_swc2_func = 0x8, 319 mm_swp_func = 0x9, 320 mm_sdc2_func = 0xa, 321 mm_sdp_func = 0xc, 322 mm_swm32_func = 0xd, 323 mm_sdm_func = 0xf, 324 }; 325 326 /* 327 * (microMIPS) POOL32C functions. 328 */ 329 enum mm_32c_func { 330 mm_pref_func = 0x2, 331 mm_ll_func = 0x3, 332 mm_swr_func = 0x9, 333 mm_sc_func = 0xb, 334 mm_lwu_func = 0xe, 335 }; 336 337 /* 338 * (microMIPS) POOL32AXF minor opcodes. 339 */ 340 enum mm_32axf_minor_op { 341 mm_mfc0_op = 0x003, 342 mm_mtc0_op = 0x00b, 343 mm_tlbp_op = 0x00d, 344 mm_jalr_op = 0x03c, 345 mm_tlbr_op = 0x04d, 346 mm_jalrhb_op = 0x07c, 347 mm_tlbwi_op = 0x08d, 348 mm_tlbwr_op = 0x0cd, 349 mm_jalrs_op = 0x13c, 350 mm_jalrshb_op = 0x17c, 351 mm_syscall_op = 0x22d, 352 mm_eret_op = 0x3cd, 353 }; 354 355 /* 356 * (microMIPS) POOL32F minor opcodes. 357 */ 358 enum mm_32f_minor_op { 359 mm_32f_00_op = 0x00, 360 mm_32f_01_op = 0x01, 361 mm_32f_02_op = 0x02, 362 mm_32f_10_op = 0x08, 363 mm_32f_11_op = 0x09, 364 mm_32f_12_op = 0x0a, 365 mm_32f_20_op = 0x10, 366 mm_32f_30_op = 0x18, 367 mm_32f_40_op = 0x20, 368 mm_32f_41_op = 0x21, 369 mm_32f_42_op = 0x22, 370 mm_32f_50_op = 0x28, 371 mm_32f_51_op = 0x29, 372 mm_32f_52_op = 0x2a, 373 mm_32f_60_op = 0x30, 374 mm_32f_70_op = 0x38, 375 mm_32f_73_op = 0x3b, 376 mm_32f_74_op = 0x3c, 377 }; 378 379 /* 380 * (microMIPS) POOL32F secondary minor opcodes. 381 */ 382 enum mm_32f_10_minor_op { 383 mm_lwxc1_op = 0x1, 384 mm_swxc1_op, 385 mm_ldxc1_op, 386 mm_sdxc1_op, 387 mm_luxc1_op, 388 mm_suxc1_op, 389 }; 390 391 enum mm_32f_func { 392 mm_lwxc1_func = 0x048, 393 mm_swxc1_func = 0x088, 394 mm_ldxc1_func = 0x0c8, 395 mm_sdxc1_func = 0x108, 396 }; 397 398 /* 399 * (microMIPS) POOL32F secondary minor opcodes. 400 */ 401 enum mm_32f_40_minor_op { 402 mm_fmovf_op, 403 mm_fmovt_op, 404 }; 405 406 /* 407 * (microMIPS) POOL32F secondary minor opcodes. 408 */ 409 enum mm_32f_60_minor_op { 410 mm_fadd_op, 411 mm_fsub_op, 412 mm_fmul_op, 413 mm_fdiv_op, 414 }; 415 416 /* 417 * (microMIPS) POOL32F secondary minor opcodes. 418 */ 419 enum mm_32f_70_minor_op { 420 mm_fmovn_op, 421 mm_fmovz_op, 422 }; 423 424 /* 425 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F. 426 */ 427 enum mm_32f_73_minor_op { 428 mm_fmov0_op = 0x01, 429 mm_fcvtl_op = 0x04, 430 mm_movf0_op = 0x05, 431 mm_frsqrt_op = 0x08, 432 mm_ffloorl_op = 0x0c, 433 mm_fabs0_op = 0x0d, 434 mm_fcvtw_op = 0x24, 435 mm_movt0_op = 0x25, 436 mm_fsqrt_op = 0x28, 437 mm_ffloorw_op = 0x2c, 438 mm_fneg0_op = 0x2d, 439 mm_cfc1_op = 0x40, 440 mm_frecip_op = 0x48, 441 mm_fceill_op = 0x4c, 442 mm_fcvtd0_op = 0x4d, 443 mm_ctc1_op = 0x60, 444 mm_fceilw_op = 0x6c, 445 mm_fcvts0_op = 0x6d, 446 mm_mfc1_op = 0x80, 447 mm_fmov1_op = 0x81, 448 mm_movf1_op = 0x85, 449 mm_ftruncl_op = 0x8c, 450 mm_fabs1_op = 0x8d, 451 mm_mtc1_op = 0xa0, 452 mm_movt1_op = 0xa5, 453 mm_ftruncw_op = 0xac, 454 mm_fneg1_op = 0xad, 455 mm_froundl_op = 0xcc, 456 mm_fcvtd1_op = 0xcd, 457 mm_froundw_op = 0xec, 458 mm_fcvts1_op = 0xed, 459 }; 460 461 /* 462 * (microMIPS) POOL16C minor opcodes. 463 */ 464 enum mm_16c_minor_op { 465 mm_lwm16_op = 0x04, 466 mm_swm16_op = 0x05, 467 mm_jr16_op = 0x18, 468 mm_jrc_op = 0x1a, 469 mm_jalr16_op = 0x1c, 470 mm_jalrs16_op = 0x1e, 471 }; 472 473 /* 474 * (microMIPS) POOL16D minor opcodes. 475 */ 476 enum mm_16d_minor_op { 477 mm_addius5_func, 478 mm_addiusp_func, 479 }; 480 481 /* 482 * (MIPS16e) opcodes. 483 */ 484 enum MIPS16e_ops { 485 MIPS16e_jal_op = 003, 486 MIPS16e_ld_op = 007, 487 MIPS16e_i8_op = 014, 488 MIPS16e_sd_op = 017, 489 MIPS16e_lb_op = 020, 490 MIPS16e_lh_op = 021, 491 MIPS16e_lwsp_op = 022, 492 MIPS16e_lw_op = 023, 493 MIPS16e_lbu_op = 024, 494 MIPS16e_lhu_op = 025, 495 MIPS16e_lwpc_op = 026, 496 MIPS16e_lwu_op = 027, 497 MIPS16e_sb_op = 030, 498 MIPS16e_sh_op = 031, 499 MIPS16e_swsp_op = 032, 500 MIPS16e_sw_op = 033, 501 MIPS16e_rr_op = 035, 502 MIPS16e_extend_op = 036, 503 MIPS16e_i64_op = 037, 504 }; 505 506 enum MIPS16e_i64_func { 507 MIPS16e_ldsp_func, 508 MIPS16e_sdsp_func, 509 MIPS16e_sdrasp_func, 510 MIPS16e_dadjsp_func, 511 MIPS16e_ldpc_func, 512 }; 513 514 enum MIPS16e_rr_func { 515 MIPS16e_jr_func, 516 }; 517 518 enum MIPS6e_i8_func { 519 MIPS16e_swrasp_func = 02, 520 }; 521 522 /* 523 * (microMIPS & MIPS16e) NOP instruction. 524 */ 525 #define MM_NOP16 0x0c00 526 527 /* 528 * Damn ... bitfields depend from byteorder :-( 529 */ 530 #ifdef __MIPSEB__ 531 #define BITFIELD_FIELD(field, more) \ 532 field; \ 533 more 534 535 #elif defined(__MIPSEL__) 536 537 #define BITFIELD_FIELD(field, more) \ 538 more \ 539 field; 540 541 #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ 542 #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" 543 #endif 544 545 struct j_format { 546 BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ 547 BITFIELD_FIELD(unsigned int target : 26, 548 ;)) 549 }; 550 551 struct i_format { /* signed immediate format */ 552 BITFIELD_FIELD(unsigned int opcode : 6, 553 BITFIELD_FIELD(unsigned int rs : 5, 554 BITFIELD_FIELD(unsigned int rt : 5, 555 BITFIELD_FIELD(signed int simmediate : 16, 556 ;)))) 557 }; 558 559 struct u_format { /* unsigned immediate format */ 560 BITFIELD_FIELD(unsigned int opcode : 6, 561 BITFIELD_FIELD(unsigned int rs : 5, 562 BITFIELD_FIELD(unsigned int rt : 5, 563 BITFIELD_FIELD(unsigned int uimmediate : 16, 564 ;)))) 565 }; 566 567 struct c_format { /* Cache (>= R6000) format */ 568 BITFIELD_FIELD(unsigned int opcode : 6, 569 BITFIELD_FIELD(unsigned int rs : 5, 570 BITFIELD_FIELD(unsigned int c_op : 3, 571 BITFIELD_FIELD(unsigned int cache : 2, 572 BITFIELD_FIELD(unsigned int simmediate : 16, 573 ;))))) 574 }; 575 576 struct r_format { /* Register format */ 577 BITFIELD_FIELD(unsigned int opcode : 6, 578 BITFIELD_FIELD(unsigned int rs : 5, 579 BITFIELD_FIELD(unsigned int rt : 5, 580 BITFIELD_FIELD(unsigned int rd : 5, 581 BITFIELD_FIELD(unsigned int re : 5, 582 BITFIELD_FIELD(unsigned int func : 6, 583 ;)))))) 584 }; 585 586 struct p_format { /* Performance counter format (R10000) */ 587 BITFIELD_FIELD(unsigned int opcode : 6, 588 BITFIELD_FIELD(unsigned int rs : 5, 589 BITFIELD_FIELD(unsigned int rt : 5, 590 BITFIELD_FIELD(unsigned int rd : 5, 591 BITFIELD_FIELD(unsigned int re : 5, 592 BITFIELD_FIELD(unsigned int func : 6, 593 ;)))))) 594 }; 595 596 struct dsp_format { /* SPEC3 DSP format instructions */ 597 BITFIELD_FIELD(unsigned int opcode : 6, 598 BITFIELD_FIELD(unsigned int base : 5, 599 BITFIELD_FIELD(unsigned int index : 5, 600 BITFIELD_FIELD(unsigned int rd : 5, 601 BITFIELD_FIELD(unsigned int op : 5, 602 BITFIELD_FIELD(unsigned int func : 6, 603 ;)))))) 604 }; 605 606 struct spec3_format { /* SPEC3 */ 607 BITFIELD_FIELD(unsigned int opcode : 6, 608 BITFIELD_FIELD(unsigned int rs : 5, 609 BITFIELD_FIELD(unsigned int rt : 5, 610 BITFIELD_FIELD(signed int simmediate : 9, 611 BITFIELD_FIELD(unsigned int ls_func : 7, 612 ;))))) 613 }; 614 615 struct f_format { /* FPU register format */ 616 BITFIELD_FIELD(unsigned int opcode : 6, 617 BITFIELD_FIELD(unsigned int : 1, 618 BITFIELD_FIELD(unsigned int fmt : 4, 619 BITFIELD_FIELD(unsigned int rt : 5, 620 BITFIELD_FIELD(unsigned int rd : 5, 621 BITFIELD_FIELD(unsigned int re : 5, 622 BITFIELD_FIELD(unsigned int func : 6, 623 ;))))))) 624 }; 625 626 struct ma_format { /* FPU multiply and add format (MIPS IV) */ 627 BITFIELD_FIELD(unsigned int opcode : 6, 628 BITFIELD_FIELD(unsigned int fr : 5, 629 BITFIELD_FIELD(unsigned int ft : 5, 630 BITFIELD_FIELD(unsigned int fs : 5, 631 BITFIELD_FIELD(unsigned int fd : 5, 632 BITFIELD_FIELD(unsigned int func : 4, 633 BITFIELD_FIELD(unsigned int fmt : 2, 634 ;))))))) 635 }; 636 637 struct b_format { /* BREAK and SYSCALL */ 638 BITFIELD_FIELD(unsigned int opcode : 6, 639 BITFIELD_FIELD(unsigned int code : 20, 640 BITFIELD_FIELD(unsigned int func : 6, 641 ;))) 642 }; 643 644 struct ps_format { /* MIPS-3D / paired single format */ 645 BITFIELD_FIELD(unsigned int opcode : 6, 646 BITFIELD_FIELD(unsigned int rs : 5, 647 BITFIELD_FIELD(unsigned int ft : 5, 648 BITFIELD_FIELD(unsigned int fs : 5, 649 BITFIELD_FIELD(unsigned int fd : 5, 650 BITFIELD_FIELD(unsigned int func : 6, 651 ;)))))) 652 }; 653 654 struct v_format { /* MDMX vector format */ 655 BITFIELD_FIELD(unsigned int opcode : 6, 656 BITFIELD_FIELD(unsigned int sel : 4, 657 BITFIELD_FIELD(unsigned int fmt : 1, 658 BITFIELD_FIELD(unsigned int vt : 5, 659 BITFIELD_FIELD(unsigned int vs : 5, 660 BITFIELD_FIELD(unsigned int vd : 5, 661 BITFIELD_FIELD(unsigned int func : 6, 662 ;))))))) 663 }; 664 665 struct msa_mi10_format { /* MSA */ 666 BITFIELD_FIELD(unsigned int opcode : 6, 667 BITFIELD_FIELD(signed int s10 : 10, 668 BITFIELD_FIELD(unsigned int rs : 5, 669 BITFIELD_FIELD(unsigned int wd : 5, 670 BITFIELD_FIELD(unsigned int func : 4, 671 BITFIELD_FIELD(unsigned int df : 2, 672 ;)))))) 673 }; 674 675 struct rel_format { /* PC-relative */ 676 BITFIELD_FIELD(unsigned int opcode : 6, 677 BITFIELD_FIELD(unsigned int rs : 5, 678 BITFIELD_FIELD(unsigned int op : 2, 679 BITFIELD_FIELD(signed int simmediate : 19, 680 ;)))) 681 }; 682 683 struct rl16_format { /* PC-relative, 16bit offset */ 684 BITFIELD_FIELD(unsigned int opcode : 6, 685 BITFIELD_FIELD(unsigned int rs : 5, 686 BITFIELD_FIELD(unsigned int op : 2, 687 BITFIELD_FIELD(unsigned int func : 3, 688 BITFIELD_FIELD(signed int simmediate : 16, 689 ;))))) 690 }; 691 692 struct rl18_format { /* PC-relative, 18bit offset */ 693 BITFIELD_FIELD(unsigned int opcode : 6, 694 BITFIELD_FIELD(unsigned int rs : 5, 695 BITFIELD_FIELD(unsigned int op : 2, 696 BITFIELD_FIELD(unsigned int unused : 1, 697 BITFIELD_FIELD(signed int simmediate : 18, 698 ;))))) 699 }; 700 701 /* 702 * microMIPS instruction formats (32-bit length) 703 * 704 * NOTE: 705 * Parenthesis denote whether the format is a microMIPS instruction or 706 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. 707 */ 708 struct fb_format { /* FPU branch format (MIPS32) */ 709 BITFIELD_FIELD(unsigned int opcode : 6, 710 BITFIELD_FIELD(unsigned int bc : 5, 711 BITFIELD_FIELD(unsigned int cc : 3, 712 BITFIELD_FIELD(unsigned int flag : 2, 713 BITFIELD_FIELD(signed int simmediate : 16, 714 ;))))) 715 }; 716 717 struct fp0_format { /* FPU multiply and add format (MIPS32) */ 718 BITFIELD_FIELD(unsigned int opcode : 6, 719 BITFIELD_FIELD(unsigned int fmt : 5, 720 BITFIELD_FIELD(unsigned int ft : 5, 721 BITFIELD_FIELD(unsigned int fs : 5, 722 BITFIELD_FIELD(unsigned int fd : 5, 723 BITFIELD_FIELD(unsigned int func : 6, 724 ;)))))) 725 }; 726 727 struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ 728 BITFIELD_FIELD(unsigned int opcode : 6, 729 BITFIELD_FIELD(unsigned int ft : 5, 730 BITFIELD_FIELD(unsigned int fs : 5, 731 BITFIELD_FIELD(unsigned int fd : 5, 732 BITFIELD_FIELD(unsigned int fmt : 3, 733 BITFIELD_FIELD(unsigned int op : 2, 734 BITFIELD_FIELD(unsigned int func : 6, 735 ;))))))) 736 }; 737 738 struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ 739 BITFIELD_FIELD(unsigned int opcode : 6, 740 BITFIELD_FIELD(unsigned int op : 5, 741 BITFIELD_FIELD(unsigned int rt : 5, 742 BITFIELD_FIELD(unsigned int fs : 5, 743 BITFIELD_FIELD(unsigned int fd : 5, 744 BITFIELD_FIELD(unsigned int func : 6, 745 ;)))))) 746 }; 747 748 struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ 749 BITFIELD_FIELD(unsigned int opcode : 6, 750 BITFIELD_FIELD(unsigned int rt : 5, 751 BITFIELD_FIELD(unsigned int fs : 5, 752 BITFIELD_FIELD(unsigned int fmt : 2, 753 BITFIELD_FIELD(unsigned int op : 8, 754 BITFIELD_FIELD(unsigned int func : 6, 755 ;)))))) 756 }; 757 758 struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ 759 BITFIELD_FIELD(unsigned int opcode : 6, 760 BITFIELD_FIELD(unsigned int fd : 5, 761 BITFIELD_FIELD(unsigned int fs : 5, 762 BITFIELD_FIELD(unsigned int cc : 3, 763 BITFIELD_FIELD(unsigned int zero : 2, 764 BITFIELD_FIELD(unsigned int fmt : 2, 765 BITFIELD_FIELD(unsigned int op : 3, 766 BITFIELD_FIELD(unsigned int func : 6, 767 ;)))))))) 768 }; 769 770 struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ 771 BITFIELD_FIELD(unsigned int opcode : 6, 772 BITFIELD_FIELD(unsigned int rt : 5, 773 BITFIELD_FIELD(unsigned int fs : 5, 774 BITFIELD_FIELD(unsigned int fmt : 3, 775 BITFIELD_FIELD(unsigned int op : 7, 776 BITFIELD_FIELD(unsigned int func : 6, 777 ;)))))) 778 }; 779 780 struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ 781 BITFIELD_FIELD(unsigned int opcode : 6, 782 BITFIELD_FIELD(unsigned int rt : 5, 783 BITFIELD_FIELD(unsigned int fs : 5, 784 BITFIELD_FIELD(unsigned int cc : 3, 785 BITFIELD_FIELD(unsigned int fmt : 3, 786 BITFIELD_FIELD(unsigned int cond : 4, 787 BITFIELD_FIELD(unsigned int func : 6, 788 ;))))))) 789 }; 790 791 struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ 792 BITFIELD_FIELD(unsigned int opcode : 6, 793 BITFIELD_FIELD(unsigned int index : 5, 794 BITFIELD_FIELD(unsigned int base : 5, 795 BITFIELD_FIELD(unsigned int fd : 5, 796 BITFIELD_FIELD(unsigned int op : 5, 797 BITFIELD_FIELD(unsigned int func : 6, 798 ;)))))) 799 }; 800 801 struct fp6_format { /* FPU madd and msub format (MIPS IV) */ 802 BITFIELD_FIELD(unsigned int opcode : 6, 803 BITFIELD_FIELD(unsigned int fr : 5, 804 BITFIELD_FIELD(unsigned int ft : 5, 805 BITFIELD_FIELD(unsigned int fs : 5, 806 BITFIELD_FIELD(unsigned int fd : 5, 807 BITFIELD_FIELD(unsigned int func : 6, 808 ;)))))) 809 }; 810 811 struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ 812 BITFIELD_FIELD(unsigned int opcode : 6, 813 BITFIELD_FIELD(unsigned int ft : 5, 814 BITFIELD_FIELD(unsigned int fs : 5, 815 BITFIELD_FIELD(unsigned int fd : 5, 816 BITFIELD_FIELD(unsigned int fr : 5, 817 BITFIELD_FIELD(unsigned int func : 6, 818 ;)))))) 819 }; 820 821 struct mm_i_format { /* Immediate format (microMIPS) */ 822 BITFIELD_FIELD(unsigned int opcode : 6, 823 BITFIELD_FIELD(unsigned int rt : 5, 824 BITFIELD_FIELD(unsigned int rs : 5, 825 BITFIELD_FIELD(signed int simmediate : 16, 826 ;)))) 827 }; 828 829 struct mm_m_format { /* Multi-word load/store format (microMIPS) */ 830 BITFIELD_FIELD(unsigned int opcode : 6, 831 BITFIELD_FIELD(unsigned int rd : 5, 832 BITFIELD_FIELD(unsigned int base : 5, 833 BITFIELD_FIELD(unsigned int func : 4, 834 BITFIELD_FIELD(signed int simmediate : 12, 835 ;))))) 836 }; 837 838 struct mm_x_format { /* Scaled indexed load format (microMIPS) */ 839 BITFIELD_FIELD(unsigned int opcode : 6, 840 BITFIELD_FIELD(unsigned int index : 5, 841 BITFIELD_FIELD(unsigned int base : 5, 842 BITFIELD_FIELD(unsigned int rd : 5, 843 BITFIELD_FIELD(unsigned int func : 11, 844 ;))))) 845 }; 846 847 /* 848 * microMIPS instruction formats (16-bit length) 849 */ 850 struct mm_b0_format { /* Unconditional branch format (microMIPS) */ 851 BITFIELD_FIELD(unsigned int opcode : 6, 852 BITFIELD_FIELD(signed int simmediate : 10, 853 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 854 ;))) 855 }; 856 857 struct mm_b1_format { /* Conditional branch format (microMIPS) */ 858 BITFIELD_FIELD(unsigned int opcode : 6, 859 BITFIELD_FIELD(unsigned int rs : 3, 860 BITFIELD_FIELD(signed int simmediate : 7, 861 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 862 ;)))) 863 }; 864 865 struct mm16_m_format { /* Multi-word load/store format */ 866 BITFIELD_FIELD(unsigned int opcode : 6, 867 BITFIELD_FIELD(unsigned int func : 4, 868 BITFIELD_FIELD(unsigned int rlist : 2, 869 BITFIELD_FIELD(unsigned int imm : 4, 870 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 871 ;))))) 872 }; 873 874 struct mm16_rb_format { /* Signed immediate format */ 875 BITFIELD_FIELD(unsigned int opcode : 6, 876 BITFIELD_FIELD(unsigned int rt : 3, 877 BITFIELD_FIELD(unsigned int base : 3, 878 BITFIELD_FIELD(signed int simmediate : 4, 879 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 880 ;))))) 881 }; 882 883 struct mm16_r3_format { /* Load from global pointer format */ 884 BITFIELD_FIELD(unsigned int opcode : 6, 885 BITFIELD_FIELD(unsigned int rt : 3, 886 BITFIELD_FIELD(signed int simmediate : 7, 887 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 888 ;)))) 889 }; 890 891 struct mm16_r5_format { /* Load/store from stack pointer format */ 892 BITFIELD_FIELD(unsigned int opcode : 6, 893 BITFIELD_FIELD(unsigned int rt : 5, 894 BITFIELD_FIELD(signed int simmediate : 5, 895 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 896 ;)))) 897 }; 898 899 /* 900 * MIPS16e instruction formats (16-bit length) 901 */ 902 struct m16e_rr { 903 BITFIELD_FIELD(unsigned int opcode : 5, 904 BITFIELD_FIELD(unsigned int rx : 3, 905 BITFIELD_FIELD(unsigned int nd : 1, 906 BITFIELD_FIELD(unsigned int l : 1, 907 BITFIELD_FIELD(unsigned int ra : 1, 908 BITFIELD_FIELD(unsigned int func : 5, 909 ;)))))) 910 }; 911 912 struct m16e_jal { 913 BITFIELD_FIELD(unsigned int opcode : 5, 914 BITFIELD_FIELD(unsigned int x : 1, 915 BITFIELD_FIELD(unsigned int imm20_16 : 5, 916 BITFIELD_FIELD(signed int imm25_21 : 5, 917 ;)))) 918 }; 919 920 struct m16e_i64 { 921 BITFIELD_FIELD(unsigned int opcode : 5, 922 BITFIELD_FIELD(unsigned int func : 3, 923 BITFIELD_FIELD(unsigned int imm : 8, 924 ;))) 925 }; 926 927 struct m16e_ri64 { 928 BITFIELD_FIELD(unsigned int opcode : 5, 929 BITFIELD_FIELD(unsigned int func : 3, 930 BITFIELD_FIELD(unsigned int ry : 3, 931 BITFIELD_FIELD(unsigned int imm : 5, 932 ;)))) 933 }; 934 935 struct m16e_ri { 936 BITFIELD_FIELD(unsigned int opcode : 5, 937 BITFIELD_FIELD(unsigned int rx : 3, 938 BITFIELD_FIELD(unsigned int imm : 8, 939 ;))) 940 }; 941 942 struct m16e_rri { 943 BITFIELD_FIELD(unsigned int opcode : 5, 944 BITFIELD_FIELD(unsigned int rx : 3, 945 BITFIELD_FIELD(unsigned int ry : 3, 946 BITFIELD_FIELD(unsigned int imm : 5, 947 ;)))) 948 }; 949 950 struct m16e_i8 { 951 BITFIELD_FIELD(unsigned int opcode : 5, 952 BITFIELD_FIELD(unsigned int func : 3, 953 BITFIELD_FIELD(unsigned int imm : 8, 954 ;))) 955 }; 956 957 union mips_instruction { 958 unsigned int word; 959 unsigned short halfword[2]; 960 unsigned char byte[4]; 961 struct j_format j_format; 962 struct i_format i_format; 963 struct u_format u_format; 964 struct c_format c_format; 965 struct r_format r_format; 966 struct p_format p_format; 967 struct dsp_format dsp_format; 968 struct spec3_format spec3_format; 969 struct f_format f_format; 970 struct ma_format ma_format; 971 struct msa_mi10_format msa_mi10_format; 972 struct rel_format rel_format; 973 struct rl16_format rl16_format; 974 struct rl18_format rl18_format; 975 struct b_format b_format; 976 struct ps_format ps_format; 977 struct v_format v_format; 978 struct fb_format fb_format; 979 struct fp0_format fp0_format; 980 struct mm_fp0_format mm_fp0_format; 981 struct fp1_format fp1_format; 982 struct mm_fp1_format mm_fp1_format; 983 struct mm_fp2_format mm_fp2_format; 984 struct mm_fp3_format mm_fp3_format; 985 struct mm_fp4_format mm_fp4_format; 986 struct mm_fp5_format mm_fp5_format; 987 struct fp6_format fp6_format; 988 struct mm_fp6_format mm_fp6_format; 989 struct mm_i_format mm_i_format; 990 struct mm_m_format mm_m_format; 991 struct mm_x_format mm_x_format; 992 struct mm_b0_format mm_b0_format; 993 struct mm_b1_format mm_b1_format; 994 struct mm16_m_format mm16_m_format ; 995 struct mm16_rb_format mm16_rb_format; 996 struct mm16_r3_format mm16_r3_format; 997 struct mm16_r5_format mm16_r5_format; 998 }; 999 1000 union mips16e_instruction { 1001 unsigned int full : 16; 1002 struct m16e_rr rr; 1003 struct m16e_jal jal; 1004 struct m16e_i64 i64; 1005 struct m16e_ri64 ri64; 1006 struct m16e_ri ri; 1007 struct m16e_rri rri; 1008 struct m16e_i8 i8; 1009 }; 1010 1011 #endif /* _UAPI_ASM_INST_H */ 1012