| /arch/arm/plat-omap/ |
| D | dmtimer.c | 71 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) in omap_dm_timer_read_reg() argument
74 return __omap_dm_timer_read(timer, reg, timer->posted); in omap_dm_timer_read_reg()
87 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, in omap_dm_timer_write_reg() argument
91 __omap_dm_timer_write(timer, reg, value, timer->posted); in omap_dm_timer_write_reg()
94 static void omap_timer_restore_context(struct omap_dm_timer *timer) in omap_timer_restore_context() argument
96 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, in omap_timer_restore_context()
97 timer->context.twer); in omap_timer_restore_context()
98 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, in omap_timer_restore_context()
99 timer->context.tcrr); in omap_timer_restore_context()
100 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, in omap_timer_restore_context()
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| /arch/arm/plat-omap/include/plat/ |
| D | dmtimer.h | 132 int omap_dm_timer_free(struct omap_dm_timer *timer);
133 void omap_dm_timer_enable(struct omap_dm_timer *timer);
134 void omap_dm_timer_disable(struct omap_dm_timer *timer);
136 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
139 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
141 int omap_dm_timer_trigger(struct omap_dm_timer *timer);
142 int omap_dm_timer_start(struct omap_dm_timer *timer);
143 int omap_dm_timer_stop(struct omap_dm_timer *timer);
145 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
146 int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
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| /arch/mips/include/asm/mach-jz4740/ |
| D | timer.h | 64 static inline void jz4740_timer_stop(unsigned int timer) in jz4740_timer_stop() argument
66 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_stop()
69 static inline void jz4740_timer_start(unsigned int timer) in jz4740_timer_start() argument
71 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); in jz4740_timer_start()
74 static inline bool jz4740_timer_is_enabled(unsigned int timer) in jz4740_timer_is_enabled() argument
76 return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer); in jz4740_timer_is_enabled()
79 static inline void jz4740_timer_enable(unsigned int timer) in jz4740_timer_enable() argument
81 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET); in jz4740_timer_enable()
84 static inline void jz4740_timer_disable(unsigned int timer) in jz4740_timer_disable() argument
86 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR); in jz4740_timer_disable()
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| /arch/s390/kernel/ |
| D | vtime.c | 36 u64 timer; in get_vtimer() local
38 asm volatile("stpt %0" : "=m" (timer)); in get_vtimer()
39 return timer; in get_vtimer()
44 u64 timer; in set_vtimer() local
49 : "=m" (timer) : "m" (expires)); in set_vtimer()
50 S390_lowcore.system_timer += S390_lowcore.last_update_timer - timer; in set_vtimer()
71 u64 timer, clock, user, system, steal; in do_account_vtime() local
73 timer = S390_lowcore.last_update_timer; in do_account_vtime()
80 S390_lowcore.system_timer += timer - S390_lowcore.last_update_timer; in do_account_vtime()
133 u64 timer, system; in vtime_account_irq_enter() local
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| /arch/arm/kvm/ |
| D | arch_timer.c | 42 static bool timer_is_armed(struct arch_timer_cpu *timer) in timer_is_armed() argument
44 return timer->armed; in timer_is_armed()
48 static void timer_arm(struct arch_timer_cpu *timer, u64 ns) in timer_arm() argument
50 timer->armed = true; in timer_arm()
51 hrtimer_start(&timer->timer, ktime_add_ns(ktime_get(), ns), in timer_arm()
55 static void timer_disarm(struct arch_timer_cpu *timer) in timer_disarm() argument
57 if (timer_is_armed(timer)) { in timer_disarm()
58 hrtimer_cancel(&timer->timer); in timer_disarm()
59 cancel_work_sync(&timer->expired); in timer_disarm()
60 timer->armed = false; in timer_disarm()
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| /arch/arm/boot/dts/ |
| D | omap2.dtsi | 87 timer2: timer@4802a000 {
88 compatible = "ti,omap2420-timer";
94 timer3: timer@48078000 {
95 compatible = "ti,omap2420-timer";
101 timer4: timer@4807a000 {
102 compatible = "ti,omap2420-timer";
108 timer5: timer@4807c000 {
109 compatible = "ti,omap2420-timer";
113 ti,timer-dsp;
116 timer6: timer@4807e000 {
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| D | integratorap.dts | 13 arm,timer-primary = &timer2;
14 arm,timer-secondary = &timer1;
26 timer0: timer@13000000 {
27 compatible = "arm,integrator-timer";
30 timer1: timer@13000100 {
31 compatible = "arm,integrator-timer";
34 timer2: timer@13000200 {
35 compatible = "arm,integrator-timer";
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| D | omap3.dtsi | 380 timer1: timer@48318000 {
381 compatible = "ti,omap3430-timer";
385 ti,timer-alwon;
388 timer2: timer@49032000 {
389 compatible = "ti,omap3430-timer";
395 timer3: timer@49034000 {
396 compatible = "ti,omap3430-timer";
402 timer4: timer@49036000 {
403 compatible = "ti,omap3430-timer";
409 timer5: timer@49038000 {
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| D | integratorcp.dts | 13 arm,timer-primary = &timer2;
14 arm,timer-secondary = &timer1;
26 timer0: timer@13000000 {
27 compatible = "arm,integrator-cp-timer";
30 timer1: timer@13000100 {
31 compatible = "arm,integrator-cp-timer";
34 timer2: timer@13000200 {
35 compatible = "arm,integrator-cp-timer";
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| D | omap5.dtsi | 45 timer {
46 compatible = "arm,armv7-timer";
505 timer1: timer@4ae18000 {
506 compatible = "ti,omap5430-timer";
510 ti,timer-alwon;
513 timer2: timer@48032000 {
514 compatible = "ti,omap5430-timer";
520 timer3: timer@48034000 {
521 compatible = "ti,omap5430-timer";
527 timer4: timer@48036000 {
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| D | am33xx.dtsi | 245 timer1: timer@44e31000 {
246 compatible = "ti,am335x-timer-1ms";
250 ti,timer-alwon;
253 timer2: timer@48040000 {
254 compatible = "ti,am335x-timer";
260 timer3: timer@48042000 {
261 compatible = "ti,am335x-timer";
267 timer4: timer@48044000 {
268 compatible = "ti,am335x-timer";
272 ti,timer-pwm;
[all …]
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| /arch/c6x/platforms/ |
| D | timer64.c | 35 static struct timer_regs __iomem *timer; variable
69 ((soc_readl(&timer->emumgt) & (0xf << 16)) >> 16)
82 u32 tcr = soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK; in timer64_config()
84 soc_writel(tcr, &timer->tcr); in timer64_config()
85 soc_writel(period - 1, &timer->prdlo); in timer64_config()
86 soc_writel(0, &timer->cntlo); in timer64_config()
88 soc_writel(tcr, &timer->tcr); in timer64_config()
99 soc_writel(soc_readl(&timer->tcr) & ~TCR_ENAMODELO_MASK, &timer->tcr); in timer64_enable()
100 soc_writel(0, &timer->prdlo); in timer64_enable()
103 val = soc_readl(&timer->tcr); in timer64_enable()
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| /arch/arm/mach-omap1/ |
| D | time.c | 74 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); in omap_mpu_timer_read() local
75 return readl(&timer->read_tim); in omap_mpu_timer_read()
80 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); in omap_mpu_set_autoreset() local
82 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); in omap_mpu_set_autoreset()
87 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); in omap_mpu_remove_autoreset() local
89 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); in omap_mpu_remove_autoreset()
95 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); in omap_mpu_timer_start() local
101 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); in omap_mpu_timer_start()
103 writel(load_val, &timer->load_tim); in omap_mpu_timer_start()
105 writel(timerflags, &timer->cntl); in omap_mpu_timer_start()
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| /arch/s390/include/asm/ |
| D | vtimer.h | 21 extern void init_virt_timer(struct vtimer_list *timer);
22 extern void add_virt_timer(struct vtimer_list *timer);
23 extern void add_virt_timer_periodic(struct vtimer_list *timer);
24 extern int mod_virt_timer(struct vtimer_list *timer, u64 expires);
25 extern int mod_virt_timer_periodic(struct vtimer_list *timer, u64 expires);
26 extern int del_virt_timer(struct vtimer_list *timer);
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| /arch/c6x/boot/dts/ |
| D | evmc6678.dts | 39 timer8: timer@2280000 {
44 timer9: timer@2290000 {
49 timer10: timer@22A0000 {
54 timer11: timer@22B0000 {
59 timer12: timer@22C0000 {
64 timer13: timer@22D0000 {
69 timer14: timer@22E0000 {
74 timer15: timer@22F0000 {
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| D | evmc6472.dts | 39 timer0: timer@25e0000 {
44 timer1: timer@25f0000 {
49 timer2: timer@2600000 {
54 timer3: timer@2610000 {
59 timer4: timer@2620000 {
64 timer5: timer@2630000 {
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| D | tms320c6678.dtsi | 78 timer8: timer@2280000 {
84 timer9: timer@2290000 {
90 timer10: timer@22A0000 {
96 timer11: timer@22B0000 {
102 timer12: timer@22C0000 {
108 timer13: timer@22D0000 {
114 timer14: timer@22E0000 {
120 timer15: timer@22F0000 {
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| /arch/cris/arch-v32/kernel/ |
| D | time.c | 41 return (u32)REG_RD(timer, regi_timer0, r_time); in read_cont_rotime()
85 data = REG_RD(timer, regi_timer0, r_tmr0_data); in get_ns_in_jiffie()
125 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); in reset_watchdog()
140 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); in stop_watchdog()
194 masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr); in timer_interrupt()
200 REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr); in timer_interrupt()
243 REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div); in cris_timer_init()
244 REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */ in cris_timer_init()
246 REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */ in cris_timer_init()
249 timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask); in cris_timer_init()
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| /arch/powerpc/oprofile/cell/ |
| D | spu_profiler.c | 137 static enum hrtimer_restart profile_spus(struct hrtimer *timer) in profile_spus() argument
186 hrtimer_forward(timer, timer->base->get_time(), kt); in profile_spus()
194 static struct hrtimer timer; variable
208 hrtimer_init(&timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in start_spu_profiling_cycles()
209 hrtimer_set_expires(&timer, kt); in start_spu_profiling_cycles()
210 timer.function = profile_spus; in start_spu_profiling_cycles()
220 hrtimer_start(&timer, kt, HRTIMER_MODE_REL); in start_spu_profiling_cycles()
244 hrtimer_cancel(&timer); in stop_spu_profiling_cycles()
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| /arch/arm/mach-omap2/ |
| D | timer.c | 216 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, in omap_dm_timer_init_one() argument
239 timer->irq = irq_of_parse_and_map(np, 0); in omap_dm_timer_init_one()
240 if (!timer->irq) in omap_dm_timer_init_one()
243 timer->io_base = of_iomap(np, 0); in omap_dm_timer_init_one()
247 if (omap_dm_timer_reserve_systimer(timer->id)) in omap_dm_timer_init_one()
250 sprintf(name, "timer%d", timer->id); in omap_dm_timer_init_one()
265 timer->irq = irq.start; in omap_dm_timer_init_one()
273 timer->io_base = ioremap(mem.start, mem.end - mem.start); in omap_dm_timer_init_one()
276 if (!timer->io_base) in omap_dm_timer_init_one()
280 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); in omap_dm_timer_init_one()
[all …]
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| /arch/x86/kernel/ |
| D | apb_timer.c | 62 struct dw_apb_clock_event_device *timer; member
159 adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0", in apbt_clockevent_register()
164 adev->timer->eoi = NULL; in apbt_clockevent_register()
167 global_clock_event = &adev->timer->ced; in apbt_clockevent_register()
172 dw_apb_clockevent_register(adev->timer); in apbt_clockevent_register()
204 if (!adev->timer) { in apbt_setup_secondary_clock()
205 adev->timer = dw_apb_clockevent_init(cpu, adev->name, in apbt_setup_secondary_clock()
208 adev->timer->eoi = NULL; in apbt_setup_secondary_clock()
210 dw_apb_clockevent_resume(adev->timer); in apbt_setup_secondary_clock()
217 dw_apb_clockevent_register(adev->timer); in apbt_setup_secondary_clock()
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| /arch/arm/mach-footbridge/ |
| D | Makefile | 17 obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o
18 obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o
19 obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
20 obj-$(CONFIG_ARCH_PERSONAL_SERVER) += personal.o dc21285-timer.o
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| /arch/microblaze/kernel/ |
| D | timer.c | 247 struct device_node *timer = NULL; in time_init() local
262 timer = of_find_node_by_phandle(be32_to_cpup(prop)); in time_init()
266 if (!timer) in time_init()
267 timer = of_find_compatible_node(NULL, NULL, in time_init()
269 BUG_ON(!timer); in time_init()
271 timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL)); in time_init()
273 irq = irq_of_parse_and_map(timer, 0); in time_init()
274 timer_num = be32_to_cpup(of_get_property(timer, in time_init()
285 timer->name, timer_baseaddr, irq); in time_init()
288 prop = of_get_property(timer, "clock-frequency", NULL); in time_init()
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| /arch/mips/include/asm/netlogic/xlr/ |
| D | pic.h | 265 nlm_pic_read_timer(uint64_t base, int timer) in nlm_pic_read_timer() argument
269 up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); in nlm_pic_read_timer()
270 low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); in nlm_pic_read_timer()
271 up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer)); in nlm_pic_read_timer()
274 low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); in nlm_pic_read_timer()
280 nlm_pic_read_timer32(uint64_t base, int timer) in nlm_pic_read_timer32() argument
282 return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer)); in nlm_pic_read_timer32()
286 nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) in nlm_pic_set_timer() argument
295 nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low); in nlm_pic_set_timer()
296 nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up); in nlm_pic_set_timer()
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| /arch/mips/lasat/ |
| D | picvue_proc.c | 30 static struct timer_list timer; variable
116 del_timer(&timer); in pvc_scroll_proc_write()
129 add_timer(&timer); in pvc_scroll_proc_write()
166 timer.expires = jiffies + scroll_interval; in pvc_proc_timerfunc()
167 add_timer(&timer); in pvc_proc_timerfunc()
178 del_timer(&timer); in pvc_proc_cleanup()
205 init_timer(&timer); in pvc_proc_init()
206 timer.function = pvc_proc_timerfunc; in pvc_proc_init()
|