Searched refs:timing (Results 1 – 25 of 45) sorted by relevance
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| /arch/avr32/mach-at32ap/ |
| D | hsmc.c | 33 const struct smc_timing *timing) in smc_set_timing() argument
62 if (timing->ncs_read_setup > 0) in smc_set_timing()
63 config->ncs_read_setup = ns2cyc(timing->ncs_read_setup); in smc_set_timing()
65 if (timing->nrd_setup > 0) in smc_set_timing()
66 config->nrd_setup = ns2cyc(timing->nrd_setup); in smc_set_timing()
68 if (timing->ncs_write_setup > 0) in smc_set_timing()
69 config->ncs_write_setup = ns2cyc(timing->ncs_write_setup); in smc_set_timing()
71 if (timing->nwe_setup > 0) in smc_set_timing()
72 config->nwe_setup = ns2cyc(timing->nwe_setup); in smc_set_timing()
74 if (timing->ncs_read_pulse > 0) in smc_set_timing()
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| /arch/arm/boot/dts/ |
| D | exynos5250-smdk5250.dts | 117 samsung,dw-mshc-sdr-timing = <2 3>;
118 samsung,dw-mshc-ddr-timing = <1 2>;
138 samsung,dw-mshc-sdr-timing = <2 3>;
139 samsung,dw-mshc-ddr-timing = <1 2>;
231 timing0: timing@0 {
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| D | cros5250-common.dtsi | 239 samsung,dw-mshc-sdr-timing = <2 3>;
240 samsung,dw-mshc-ddr-timing = <1 2>;
260 samsung,dw-mshc-sdr-timing = <2 3>;
261 samsung,dw-mshc-ddr-timing = <1 2>;
279 samsung,dw-mshc-sdr-timing = <2 3>;
280 samsung,dw-mshc-ddr-timing = <1 2>;
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| D | exynos4412-odroidx.dts | 54 samsung,dw-mshc-sdr-timing = <2 3>;
55 samsung,dw-mshc-ddr-timing = <1 2>;
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| D | atlas6-evb.dts | 74 timing = <0x88>;
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| D | exynos5250-arndale.dts | 328 samsung,dw-mshc-sdr-timing = <2 3>;
329 samsung,dw-mshc-ddr-timing = <1 2>;
350 samsung,dw-mshc-sdr-timing = <2 3>;
351 samsung,dw-mshc-ddr-timing = <1 2>;
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| D | exynos4412-origen.dts | 60 samsung,dw-mshc-sdr-timing = <2 3>;
61 samsung,dw-mshc-ddr-timing = <1 2>;
83 timing0: timing {
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| /arch/avr32/mach-at32ap/include/mach/ |
| D | smc.h | 108 const struct smc_timing *timing);
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| /arch/mips/include/asm/mach-rc32434/ |
| D | rb.h | 65 u32 timing; member
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| /arch/cris/arch-v32/mach-a3/ |
| D | Kconfig | 27 hex "DDR2 SDRAM timing"
30 SDRAM timing parameters.
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| D | dram_init.S | 73 ; Set timing
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| /arch/c6x/kernel/ |
| D | vectors.S | 12 ; At RESET the processor sets up the DRAM timing parameters and
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| /arch/powerpc/kvm/ |
| D | Makefile | 18 obj-$(CONFIG_KVM_EXIT_TIMING) += timing.o
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| D | Kconfig | 113 bool "Detailed exit timing"
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| /arch/arm/mach-sa1100/ |
| D | sleep.S | 50 @ Adjust memory timing before lowering CPU clock
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| /arch/cris/arch-v32/mach-fs/ |
| D | dram_init.S | 64 ; Set timing parameters (refresh off to avoid Guinness TR 83)
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| /arch/arm/mach-exynos/ |
| D | mach-smdk4x12.c | 252 .timing = {
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| D | mach-smdkv310.c | 165 .timing = {
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| /arch/cris/arch-v10/lib/ |
| D | dram_init.S | 86 ; Set timing parameters. Starts master clock
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| /arch/arm/mach-s3c24xx/ |
| D | Kconfig | 213 Internal node to select io timing code that is common to the s3c2410
220 Internal node to select timing code that is common to the s3c2410
229 Intel node to select io timing code that is common to the s3c2412
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| /arch/arm/mach-at91/ |
| D | Kconfig | 203 reduce timing errors caused by rounding.
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| /arch/mips/cavium-octeon/ |
| D | octeon_3xxx.dts | 62 /* Fix rx and tx clock transition timing */
74 /* Fix rx and tx clock transition timing */
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| /arch/arm/mach-davinci/ |
| D | board-da830-evm.c | 378 .timing = &da830_evm_nandflash_timing,
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| /arch/mips/ |
| D | Kconfig.debug | 125 bool "Enable spinlock timing tests in debugfs"
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| /arch/blackfin/include/asm/ |
| D | bfin_can.h | 78 __BFP(timing); /* offset 0x84 */
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