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Searched refs:write_aux_reg (Results 1 – 9 of 9) sorted by relevance

/arch/arc/mm/
Dtlb.c117 write_aux_reg(ARC_REG_TLBPD1, 0); in __tlb_entry_erase()
118 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()
119 write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite); in __tlb_entry_erase()
127 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); in tlb_entry_erase()
128 write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe); in tlb_entry_erase()
176 write_aux_reg(ARC_REG_TLBINDEX, 0xa); in utlb_invalidate()
179 write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB); in utlb_invalidate()
197 write_aux_reg(ARC_REG_TLBPD1, 0); in local_flush_tlb_all()
198 write_aux_reg(ARC_REG_TLBPD0, 0); in local_flush_tlb_all()
202 write_aux_reg(ARC_REG_TLBINDEX, entry); in local_flush_tlb_all()
[all …]
Dcache_arc700.c177 write_aux_reg(ARC_REG_IC_CTRL, temp); in arc_cache_init()
207 write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE); in arc_cache_init()
210 write_aux_reg(ARC_REG_DC_FLSH, 0x1); in arc_cache_init()
212 write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE); in arc_cache_init()
254 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH); in __dc_entire_op()
262 write_aux_reg(aux, 0x1); in __dc_entire_op()
269 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH); in __dc_entire_op()
309 write_aux_reg(ARC_REG_DC_PTAG, paddr); in __dc_line_loop()
311 write_aux_reg(aux_reg, vaddr); in __dc_line_loop()
315 write_aux_reg(aux_reg, paddr); in __dc_line_loop()
[all …]
/arch/arc/kernel/
Dtime.c110 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); in arc_counter_setup()
111 write_aux_reg(ARC_REG_TIMER1_CNT, 0); in arc_counter_setup()
112 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); in arc_counter_setup()
140 write_aux_reg(ARC_REG_TIMER0_LIMIT, limit); in arc_timer_event_setup()
141 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ in arc_timer_event_setup()
143 write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); in arc_timer_event_setup()
160 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); in arc_timer_event_ack()
Dirq.c35 write_aux_reg(AUX_INTR_VEC_BASE, _int_vec_base_lds); in arc_init_IRQ()
38 write_aux_reg(AUX_IENABLE, 0); in arc_init_IRQ()
53 write_aux_reg(AUX_IRQ_LEV, level_mask); in arc_init_IRQ()
/arch/arc/include/asm/
Dmmu_context.h125 write_aux_reg(ARC_REG_PID, asid_cache | MMU_ENABLE); in get_new_mmu_context()
152 write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd); in switch_mm()
174 write_aux_reg(ARC_REG_PID, next->context.asid | MMU_ENABLE); in switch_mm()
203 write_aux_reg(ARC_REG_SCRATCH_DATA0, next->pgd); in activate_mm()
Dirqflags.h120 write_aux_reg(AUX_IENABLE, ienb); in arch_mask_irq()
129 write_aux_reg(AUX_IENABLE, ienb); in arch_unmask_irq()
Darcregs.h195 #define write_aux_reg(reg_immed, val) \ macro
216 #define write_aux_reg(reg_imm, val) \ macro
262 write_aux_reg(reg, tmp); \
/arch/arc/plat-arcfpga/
Dsmp.c33 write_aux_reg(ARC_AUX_XTL_REG_PARAM, pc); in iss_model_smp_wakeup_cpu()
36 write_aux_reg(ARC_AUX_XTL_REG_CMD, in iss_model_smp_wakeup_cpu()
40 write_aux_reg(ARC_AUX_XTL_REG_CMD, in iss_model_smp_wakeup_cpu()
/arch/arc/plat-arcfpga/include/plat/
Dsmp.h57 write_aux_reg(ARC_AUX_IDU_REG_CMD, __val); \
60 #define IDU_SET_PARAM(par) write_aux_reg(ARC_AUX_IDU_REG_PARAM, par)