| /arch/x86/crypto/ |
| D | glue_helper-asm-avx.S | 18 #define load_8way(src, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
24 vmovdqu (5*16)(src), x5; \
28 #define store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
34 vmovdqu x5, (5*16)(dst); \
38 #define store_cbc_8way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
43 vpxor (4*16)(src), x5, x5; \
46 store_8way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
54 #define load_ctr_8way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2) \ argument
73 vpshufb t1, x7, x5; \
82 #define store_ctr_8way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
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| D | glue_helper-asm-avx2.S | 13 #define load_16way(src, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
19 vmovdqu (5*32)(src), x5; \
23 #define store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
29 vmovdqu x5, (5*32)(dst); \
33 #define store_cbc_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7, t0) \ argument
41 vpxor (4*32+16)(src), x5, x5; \
44 store_16way(dst, x0, x1, x2, x3, x4, x5, x6, x7);
60 #define load_ctr_16way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t0x, t1, \ argument
84 vpshufb t1, t2, x5; \
93 #define store_ctr_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7) \ argument
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| D | salsa20-x86_64-asm_64.S | 113 # x5 = j4
115 # x4 = x5
117 # (uint64) x5 >>= 32
119 # x5_stack = x5
161 # x5 = x5_stack
169 # b = x1 + x5
181 # b = x5 + x9
209 # x5 ^= b
213 # x5_stack = x5
269 # x5 = x5_stack
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| D | camellia-aesni-avx-asm_64.S | 49 #define roundsm16(x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2, t3, t4, t5, t6, \ argument
65 vpshufb t4, x5, x5; \
77 filter_8bit(x5, t0, t1, t7, t6); \
92 vaesenclast t4, x5, x5; \
108 filter_8bit(x5, t2, t3, t7, t6); \
133 vpxor x5, x0, x0; \
139 vpxor x3, x5, x5; \
145 vpxor x5, x2, x2; \
149 vpxor x0, x5, x5; \
160 vpxor t2, x5, x5; \
[all …]
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| D | camellia-aesni-avx2-asm_64.S | 76 #define roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2, t3, t4, t5, t6, \ argument
92 vpshufb t4, x5, x5; \
104 filter_8bit(x5, t0, t1, t7, t6); \
119 vaesenclast256(t4, x5, t5); \
135 filter_8bit(x5, t2, t3, t7, t6); \
160 vpxor x5, x0, x0; \
166 vpxor x3, x5, x5; \
172 vpxor x5, x2, x2; \
176 vpxor x0, x5, x5; \
197 vpxor t2, x5, x5; \
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| D | salsa20-i586-asm_32.S | 154 # x5 = in5
196 # s = x5
209 # x5 = s
327 # s ^= x5
343 # x5 = s
459 # s ^= x5
473 # x5 = s
591 # s ^= x5
607 # x5 = s
723 # s ^= x5
[all …]
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| /arch/arm/boot/dts/ |
| D | imx51.dtsi | 404 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
405 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
406 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
407 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
408 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
409 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
410 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
411 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
412 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
413 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
[all …]
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| D | at91sam9x5ek.dtsi | 63 <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */
70 <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */
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| D | sama5d3xdm.dtsi | 36 <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */
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| D | at91sam9g20ek_2mmc.dts | 34 <2 2 0x0 0x5>; /* PC2 gpio CD pin pull up and deglitch */
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| D | sama5d3xmb.dtsi | 90 <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */
95 <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */
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| D | at91sam9m10g45ek.dts | 93 <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */
100 <3 11 0x0 0x5 /* PD11 gpio CD pin pull up and deglitch */
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| D | exynos4212.dtsi | 56 <0x5 0 &gic 1 12 0>;
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| /arch/arm64/crypto/ |
| D | aes-modes.S | 117 enc_prepare w3, x2, x5
139 encrypt_block v0, w3, x2, x5, w6
153 dec_prepare w3, x2, x5
175 decrypt_block v0, w3, x2, x5, w6
195 ld1 {v0.16b}, [x5] /* get iv */
196 enc_prepare w3, x2, x5
201 encrypt_block v0, w3, x2, x5, w6
213 ld1 {v7.16b}, [x5] /* get iv */
214 dec_prepare w3, x2, x5
251 decrypt_block v0, w3, x2, x5, w6
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| D | aes-ce-ccm-core.S | 129 ld1 {v0.2d}, [x5] /* load mac */
181 st1 {v0.2d}, [x5] /* store mac */
187 st1 {v0.2d}, [x5] /* store mac */
200 strb w7, [x5], #1 /* store mac byte */
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| /arch/powerpc/boot/dts/ |
| D | mpc8568mds.dts | 35 0x5 0x0 0xf8010000 0x00008000>;
56 reg = <0x5 0x1>;
164 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
165 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
166 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
167 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
168 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
169 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
170 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
171 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
[all …]
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| D | sbc8548.dts | 30 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
58 reg = <0x5 0x0 0x00b10000>;
60 0x0 0x0 0x5 0x000000 0x1fff /* LED */
61 0x1 0x0 0x5 0x100000 0x1fff /* Switches */
62 0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */
63 0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */
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| D | sbc8548-altflash.dts | 33 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
61 reg = <0x5 0x0 0x00b10000>;
63 0x0 0x0 0x5 0x000000 0x1fff /* LED */
64 0x1 0x0 0x5 0x100000 0x1fff /* Switches */
65 0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */
66 0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */
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| D | mpc5121ads.dts | 76 reg = <0x2 0xa 0x5>;
171 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
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| /arch/arm64/mm/ |
| D | proc.S | 93 mrs x5, mair_el1
102 stp x4, x5, [x0, #16]
125 ldp x4, x5, [x0, #16]
133 msr mair_el1, x5
194 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
199 msr mair_el1, x5
203 adr x5, crval
204 ldp w5, w6, [x5]
206 bic x0, x0, x5 // clear bits
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| /arch/arm64/kernel/ |
| D | head.S | 299 ldr x5, =vectors
300 msr vbar_el1, x5
404 create_pgd_entry x25, x0, x3, x5, x6
406 mov x5, x3 // __pa(KERNEL_START)
408 create_block_map x0, x7, x3, x5, x6
414 mov x5, #PAGE_OFFSET
415 create_pgd_entry x26, x0, x5, x3, x6
418 create_block_map x0, x7, x3, x5, x6
427 sub x5, x3, x24 // subtract PHYS_OFFSET
428 tst x5, #~((1 << 29) - 1) // within 512MB?
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| D | sys32.S | 62 orr x3, x4, x5, lsl #32
67 orr x3, x4, x5, lsl #32
90 orr x2, x4, x5, lsl #32
97 orr x3, x4, x5, lsl #32
103 orr x3, x4, x5, lsl #32
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| D | sleep.S | 84 compute_mpidr_hash x8, x3, x4, x5, x6, x7, x10
135 ldr x5, [x4]
136 add x8, x4, x5 // x8 = struct mpidr_hash phys address
141 compute_mpidr_hash x7, x3, x4, x5, x6, x1, x2
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| /arch/arm64/lib/ |
| D | copy_page.S | 33 ldp x4, x5, [x1, #16]
39 stnp x4, x5, [x0, #16]
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| /arch/sparc/lib/ |
| D | NG2memcpy.S | 82 #define FREG_FROB(x0, x1, x2, x3, x4, x5, x6, x7, x8) \ argument
87 faligndata %x4, %x5, %f8; \
88 faligndata %x5, %x6, %f10; \
112 #define FREG_MOVE_6(x0, x1, x2, x3, x4, x5) \ argument
118 fsrc2 %x5, %f10;
119 #define FREG_MOVE_7(x0, x1, x2, x3, x4, x5, x6) \ argument
125 fsrc2 %x5, %f10; \
127 #define FREG_MOVE_8(x0, x1, x2, x3, x4, x5, x6, x7) \ argument
133 fsrc2 %x5, %f10; \
156 #define FREG_LOAD_6(base, x0, x1, x2, x3, x4, x5) \ argument
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