1 /*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2012 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8 #ifndef __QL4_DEF_H
9 #define __QL4_DEF_H
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/dmapool.h>
21 #include <linux/mempool.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/mutex.h>
27 #include <linux/aer.h>
28 #include <linux/bsg-lib.h>
29
30 #include <net/tcp.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/scsi_device.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <scsi/scsi_transport.h>
36 #include <scsi/scsi_transport_iscsi.h>
37 #include <scsi/scsi_bsg_iscsi.h>
38 #include <scsi/scsi_netlink.h>
39 #include <scsi/libiscsi.h>
40
41 #include "ql4_dbg.h"
42 #include "ql4_nx.h"
43 #include "ql4_fw.h"
44 #include "ql4_nvram.h"
45 #include "ql4_83xx.h"
46
47 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
48 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
49 #endif
50
51 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
52 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
53 #endif
54
55 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
56 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
57 #endif
58
59 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
60 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
61 #endif
62
63 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
64 #define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032
65 #endif
66
67 #define ISP4XXX_PCI_FN_1 0x1
68 #define ISP4XXX_PCI_FN_2 0x3
69
70 #define QLA_SUCCESS 0
71 #define QLA_ERROR 1
72
73 /*
74 * Data bit definitions
75 */
76 #define BIT_0 0x1
77 #define BIT_1 0x2
78 #define BIT_2 0x4
79 #define BIT_3 0x8
80 #define BIT_4 0x10
81 #define BIT_5 0x20
82 #define BIT_6 0x40
83 #define BIT_7 0x80
84 #define BIT_8 0x100
85 #define BIT_9 0x200
86 #define BIT_10 0x400
87 #define BIT_11 0x800
88 #define BIT_12 0x1000
89 #define BIT_13 0x2000
90 #define BIT_14 0x4000
91 #define BIT_15 0x8000
92 #define BIT_16 0x10000
93 #define BIT_17 0x20000
94 #define BIT_18 0x40000
95 #define BIT_19 0x80000
96 #define BIT_20 0x100000
97 #define BIT_21 0x200000
98 #define BIT_22 0x400000
99 #define BIT_23 0x800000
100 #define BIT_24 0x1000000
101 #define BIT_25 0x2000000
102 #define BIT_26 0x4000000
103 #define BIT_27 0x8000000
104 #define BIT_28 0x10000000
105 #define BIT_29 0x20000000
106 #define BIT_30 0x40000000
107 #define BIT_31 0x80000000
108
109 /**
110 * Macros to help code, maintain, etc.
111 **/
112 #define ql4_printk(level, ha, format, arg...) \
113 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
114
115
116 /*
117 * Host adapter default definitions
118 ***********************************/
119 #define MAX_HBAS 16
120 #define MAX_BUSES 1
121 #define MAX_TARGETS MAX_DEV_DB_ENTRIES
122 #define MAX_LUNS 0xffff
123 #define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
124 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
125 #define MAX_PDU_ENTRIES 32
126 #define INVALID_ENTRY 0xFFFF
127 #define MAX_CMDS_TO_RISC 1024
128 #define MAX_SRBS MAX_CMDS_TO_RISC
129 #define MBOX_AEN_REG_COUNT 8
130 #define MAX_INIT_RETRIES 5
131
132 /*
133 * Buffer sizes
134 */
135 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
136 #define RESPONSE_QUEUE_DEPTH 64
137 #define QUEUE_SIZE 64
138 #define DMA_BUFFER_SIZE 512
139 #define IOCB_HIWAT_CUSHION 4
140
141 /*
142 * Misc
143 */
144 #define MAC_ADDR_LEN 6 /* in bytes */
145 #define IP_ADDR_LEN 4 /* in bytes */
146 #define IPv6_ADDR_LEN 16 /* IPv6 address size */
147 #define DRIVER_NAME "qla4xxx"
148
149 #define MAX_LINKED_CMDS_PER_LUN 3
150 #define MAX_REQS_SERVICED_PER_INTR 1
151
152 #define ISCSI_IPADDR_SIZE 4 /* IP address size */
153 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
154 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
155
156 #define QL4_SESS_RECOVERY_TMO 120 /* iSCSI session */
157 /* recovery timeout */
158
159 #define LSDW(x) ((u32)((u64)(x)))
160 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
161
162 #define DEV_DB_NON_PERSISTENT 0
163 #define DEV_DB_PERSISTENT 1
164
165 #define COPY_ISID(dst_isid, src_isid) { \
166 int i, j; \
167 for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \
168 dst_isid[i++] = src_isid[j--]; \
169 }
170
171 #define SET_BITVAL(o, n, v) { \
172 if (o) \
173 n |= v; \
174 else \
175 n &= ~v; \
176 }
177
178 /*
179 * Retry & Timeout Values
180 */
181 #define MBOX_TOV 60
182 #define SOFT_RESET_TOV 30
183 #define RESET_INTR_TOV 3
184 #define SEMAPHORE_TOV 10
185 #define ADAPTER_INIT_TOV 30
186 #define ADAPTER_RESET_TOV 180
187 #define EXTEND_CMD_TOV 60
188 #define WAIT_CMD_TOV 30
189 #define EH_WAIT_CMD_TOV 120
190 #define FIRMWARE_UP_TOV 60
191 #define RESET_FIRMWARE_TOV 30
192 #define LOGOUT_TOV 10
193 #define IOCB_TOV_MARGIN 10
194 #define RELOGIN_TOV 18
195 #define ISNS_DEREG_TOV 5
196 #define HBA_ONLINE_TOV 30
197 #define DISABLE_ACB_TOV 30
198 #define IP_CONFIG_TOV 30
199 #define LOGIN_TOV 12
200 #define BOOT_LOGIN_RESP_TOV 60
201
202 #define MAX_RESET_HA_RETRIES 2
203 #define FW_ALIVE_WAIT_TOV 3
204
205 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
206
207 /*
208 * SCSI Request Block structure (srb) that is placed
209 * on cmd->SCp location of every I/O [We have 22 bytes available]
210 */
211 struct srb {
212 struct list_head list; /* (8) */
213 struct scsi_qla_host *ha; /* HA the SP is queued on */
214 struct ddb_entry *ddb;
215 uint16_t flags; /* (1) Status flags. */
216
217 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
218 #define SRB_GOT_SENSE BIT_4 /* sense data received. */
219 uint8_t state; /* (1) Status flags. */
220
221 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
222 #define SRB_FREE_STATE 1
223 #define SRB_ACTIVE_STATE 3
224 #define SRB_ACTIVE_TIMEOUT_STATE 4
225 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
226
227 struct scsi_cmnd *cmd; /* (4) SCSI command block */
228 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
229 struct kref srb_ref; /* reference count for this srb */
230 uint8_t err_id; /* error id */
231 #define SRB_ERR_PORT 1 /* Request failed because "port down" */
232 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
233 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
234 #define SRB_ERR_OTHER 4
235
236 uint16_t reserved;
237 uint16_t iocb_tov;
238 uint16_t iocb_cnt; /* Number of used iocbs */
239 uint16_t cc_stat;
240
241 /* Used for extended sense / status continuation */
242 uint8_t *req_sense_ptr;
243 uint16_t req_sense_len;
244 uint16_t reserved2;
245 };
246
247 /* Mailbox request block structure */
248 struct mrb {
249 struct scsi_qla_host *ha;
250 struct mbox_cmd_iocb *mbox;
251 uint32_t mbox_cmd;
252 uint16_t iocb_cnt; /* Number of used iocbs */
253 uint32_t pid;
254 };
255
256 /*
257 * Asynchronous Event Queue structure
258 */
259 struct aen {
260 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
261 };
262
263 struct ql4_aen_log {
264 int count;
265 struct aen entry[MAX_AEN_ENTRIES];
266 };
267
268 /*
269 * Device Database (DDB) structure
270 */
271 struct ddb_entry {
272 struct scsi_qla_host *ha;
273 struct iscsi_cls_session *sess;
274 struct iscsi_cls_conn *conn;
275
276 uint16_t fw_ddb_index; /* DDB firmware index */
277 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
278 uint16_t ddb_type;
279 #define FLASH_DDB 0x01
280
281 struct dev_db_entry fw_ddb_entry;
282 int (*unblock_sess)(struct iscsi_cls_session *cls_session);
283 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
284 struct ddb_entry *ddb_entry, uint32_t state);
285
286 /* Driver Re-login */
287 unsigned long flags; /* DDB Flags */
288 uint16_t default_relogin_timeout; /* Max time to wait for
289 * relogin to complete */
290 atomic_t retry_relogin_timer; /* Min Time between relogins
291 * (4000 only) */
292 atomic_t relogin_timer; /* Max Time to wait for
293 * relogin to complete */
294 atomic_t relogin_retry_count; /* Num of times relogin has been
295 * retried */
296 uint32_t default_time2wait; /* Default Min time between
297 * relogins (+aens) */
298 uint16_t chap_tbl_idx;
299 };
300
301 struct qla_ddb_index {
302 struct list_head list;
303 uint16_t fw_ddb_idx;
304 struct dev_db_entry fw_ddb;
305 uint8_t flash_isid[6];
306 };
307
308 #define DDB_IPADDR_LEN 64
309
310 struct ql4_tuple_ddb {
311 int port;
312 int tpgt;
313 char ip_addr[DDB_IPADDR_LEN];
314 char iscsi_name[ISCSI_NAME_SIZE];
315 uint16_t options;
316 #define DDB_OPT_IPV6 0x0e0e
317 #define DDB_OPT_IPV4 0x0f0f
318 uint8_t isid[6];
319 };
320
321 /*
322 * DDB states.
323 */
324 #define DDB_STATE_DEAD 0 /* We can no longer talk to
325 * this device */
326 #define DDB_STATE_ONLINE 1 /* Device ready to accept
327 * commands */
328 #define DDB_STATE_MISSING 2 /* Device logged off, trying
329 * to re-login */
330
331 /*
332 * DDB flags.
333 */
334 #define DF_RELOGIN 0 /* Relogin to device */
335 #define DF_BOOT_TGT 1 /* Boot target entry */
336 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
337 #define DF_FO_MASKED 3
338
339 enum qla4_work_type {
340 QLA4_EVENT_AEN,
341 QLA4_EVENT_PING_STATUS,
342 };
343
344 struct qla4_work_evt {
345 struct list_head list;
346 enum qla4_work_type type;
347 union {
348 struct {
349 enum iscsi_host_event_code code;
350 uint32_t data_size;
351 uint8_t data[0];
352 } aen;
353 struct {
354 uint32_t status;
355 uint32_t pid;
356 uint32_t data_size;
357 uint8_t data[0];
358 } ping;
359 } u;
360 };
361
362 struct ql82xx_hw_data {
363 /* Offsets for flash/nvram access (set to ~0 if not used). */
364 uint32_t flash_conf_off;
365 uint32_t flash_data_off;
366
367 uint32_t fdt_wrt_disable;
368 uint32_t fdt_erase_cmd;
369 uint32_t fdt_block_size;
370 uint32_t fdt_unprotect_sec_cmd;
371 uint32_t fdt_protect_sec_cmd;
372
373 uint32_t flt_region_flt;
374 uint32_t flt_region_fdt;
375 uint32_t flt_region_boot;
376 uint32_t flt_region_bootload;
377 uint32_t flt_region_fw;
378
379 uint32_t flt_iscsi_param;
380 uint32_t flt_region_chap;
381 uint32_t flt_chap_size;
382 uint32_t flt_region_ddb;
383 uint32_t flt_ddb_size;
384 };
385
386 struct qla4_8xxx_legacy_intr_set {
387 uint32_t int_vec_bit;
388 uint32_t tgt_status_reg;
389 uint32_t tgt_mask_reg;
390 uint32_t pci_int_reg;
391 };
392
393 /* MSI-X Support */
394
395 #define QLA_MSIX_DEFAULT 0x00
396 #define QLA_MSIX_RSP_Q 0x01
397
398 #define QLA_MSIX_ENTRIES 2
399 #define QLA_MIDX_DEFAULT 0
400 #define QLA_MIDX_RSP_Q 1
401
402 struct ql4_msix_entry {
403 int have_irq;
404 uint16_t msix_vector;
405 uint16_t msix_entry;
406 };
407
408 /*
409 * ISP Operations
410 */
411 struct isp_operations {
412 int (*iospace_config) (struct scsi_qla_host *ha);
413 void (*pci_config) (struct scsi_qla_host *);
414 void (*disable_intrs) (struct scsi_qla_host *);
415 void (*enable_intrs) (struct scsi_qla_host *);
416 int (*start_firmware) (struct scsi_qla_host *);
417 int (*restart_firmware) (struct scsi_qla_host *);
418 irqreturn_t (*intr_handler) (int , void *);
419 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
420 int (*need_reset) (struct scsi_qla_host *);
421 int (*reset_chip) (struct scsi_qla_host *);
422 int (*reset_firmware) (struct scsi_qla_host *);
423 void (*queue_iocb) (struct scsi_qla_host *);
424 void (*complete_iocb) (struct scsi_qla_host *);
425 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
426 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
427 int (*get_sys_info) (struct scsi_qla_host *);
428 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
429 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
430 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
431 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
432 int (*idc_lock) (struct scsi_qla_host *);
433 void (*idc_unlock) (struct scsi_qla_host *);
434 void (*rom_lock_recovery) (struct scsi_qla_host *);
435 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
436 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
437 };
438
439 struct ql4_mdump_size_table {
440 uint32_t size;
441 uint32_t size_cmask_02;
442 uint32_t size_cmask_04;
443 uint32_t size_cmask_08;
444 uint32_t size_cmask_10;
445 uint32_t size_cmask_FF;
446 uint32_t version;
447 };
448
449 /*qla4xxx ipaddress configuration details */
450 struct ipaddress_config {
451 uint16_t ipv4_options;
452 uint16_t tcp_options;
453 uint16_t ipv4_vlan_tag;
454 uint8_t ipv4_addr_state;
455 uint8_t ip_address[IP_ADDR_LEN];
456 uint8_t subnet_mask[IP_ADDR_LEN];
457 uint8_t gateway[IP_ADDR_LEN];
458 uint32_t ipv6_options;
459 uint32_t ipv6_addl_options;
460 uint8_t ipv6_link_local_state;
461 uint8_t ipv6_addr0_state;
462 uint8_t ipv6_addr1_state;
463 uint8_t ipv6_default_router_state;
464 uint16_t ipv6_vlan_tag;
465 struct in6_addr ipv6_link_local_addr;
466 struct in6_addr ipv6_addr0;
467 struct in6_addr ipv6_addr1;
468 struct in6_addr ipv6_default_router_addr;
469 uint16_t eth_mtu_size;
470 uint16_t ipv4_port;
471 uint16_t ipv6_port;
472 };
473
474 #define QL4_CHAP_MAX_NAME_LEN 256
475 #define QL4_CHAP_MAX_SECRET_LEN 100
476 #define LOCAL_CHAP 0
477 #define BIDI_CHAP 1
478
479 struct ql4_chap_format {
480 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
481 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
482 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
483 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
484 u16 intr_chap_name_length;
485 u16 intr_secret_length;
486 u16 target_chap_name_length;
487 u16 target_secret_length;
488 };
489
490 struct ip_address_format {
491 u8 ip_type;
492 u8 ip_address[16];
493 };
494
495 struct ql4_conn_info {
496 u16 dest_port;
497 struct ip_address_format dest_ipaddr;
498 struct ql4_chap_format chap;
499 };
500
501 struct ql4_boot_session_info {
502 u8 target_name[224];
503 struct ql4_conn_info conn_list[1];
504 };
505
506 struct ql4_boot_tgt_info {
507 struct ql4_boot_session_info boot_pri_sess;
508 struct ql4_boot_session_info boot_sec_sess;
509 };
510
511 /*
512 * Linux Host Adapter structure
513 */
514 struct scsi_qla_host {
515 /* Linux adapter configuration data */
516 unsigned long flags;
517
518 #define AF_ONLINE 0 /* 0x00000001 */
519 #define AF_INIT_DONE 1 /* 0x00000002 */
520 #define AF_MBOX_COMMAND 2 /* 0x00000004 */
521 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
522 #define AF_ST_DISCOVERY_IN_PROGRESS 4 /* 0x00000010 */
523 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
524 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
525 #define AF_LINK_UP 8 /* 0x00000100 */
526 #define AF_LOOPBACK 9 /* 0x00000200 */
527 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
528 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
529 #define AF_HA_REMOVAL 12 /* 0x00001000 */
530 #define AF_INTx_ENABLED 15 /* 0x00008000 */
531 #define AF_MSI_ENABLED 16 /* 0x00010000 */
532 #define AF_MSIX_ENABLED 17 /* 0x00020000 */
533 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
534 #define AF_FW_RECOVERY 19 /* 0x00080000 */
535 #define AF_EEH_BUSY 20 /* 0x00100000 */
536 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
537 #define AF_BUILD_DDB_LIST 22 /* 0x00400000 */
538 #define AF_82XX_FW_DUMPED 24 /* 0x01000000 */
539 #define AF_8XXX_RST_OWNER 25 /* 0x02000000 */
540 #define AF_82XX_DUMP_READING 26 /* 0x04000000 */
541 #define AF_83XX_NO_FW_DUMP 27 /* 0x08000000 */
542 #define AF_83XX_IOCB_INTR_ON 28 /* 0x10000000 */
543 #define AF_83XX_MBOX_INTR_ON 29 /* 0x20000000 */
544
545 unsigned long dpc_flags;
546
547 #define DPC_RESET_HA 1 /* 0x00000002 */
548 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
549 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
550 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
551 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
552 #define DPC_ISNS_RESTART 7 /* 0x00000080 */
553 #define DPC_AEN 9 /* 0x00000200 */
554 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
555 #define DPC_LINK_CHANGED 18 /* 0x00040000 */
556 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */
557 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
558 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
559 #define DPC_POST_IDC_ACK 23 /* 0x00200000 */
560
561 struct Scsi_Host *host; /* pointer to host data */
562 uint32_t tot_ddbs;
563
564 uint16_t iocb_cnt;
565 uint16_t iocb_hiwat;
566
567 /* SRB cache. */
568 #define SRB_MIN_REQ 128
569 mempool_t *srb_mempool;
570
571 /* pci information */
572 struct pci_dev *pdev;
573
574 struct isp_reg __iomem *reg; /* Base I/O address */
575 unsigned long pio_address;
576 unsigned long pio_length;
577 #define MIN_IOBASE_LEN 0x100
578
579 uint16_t req_q_count;
580
581 unsigned long host_no;
582
583 /* NVRAM registers */
584 struct eeprom_data *nvram;
585 spinlock_t hardware_lock ____cacheline_aligned;
586 uint32_t eeprom_cmd_data;
587
588 /* Counters for general statistics */
589 uint64_t isr_count;
590 uint64_t adapter_error_count;
591 uint64_t device_error_count;
592 uint64_t total_io_count;
593 uint64_t total_mbytes_xferred;
594 uint64_t link_failure_count;
595 uint64_t invalid_crc_count;
596 uint32_t bytes_xfered;
597 uint32_t spurious_int_count;
598 uint32_t aborted_io_count;
599 uint32_t io_timeout_count;
600 uint32_t mailbox_timeout_count;
601 uint32_t seconds_since_last_intr;
602 uint32_t seconds_since_last_heartbeat;
603 uint32_t mac_index;
604
605 /* Info Needed for Management App */
606 /* --- From GetFwVersion --- */
607 uint32_t firmware_version[2];
608 uint32_t patch_number;
609 uint32_t build_number;
610 uint32_t board_id;
611
612 /* --- From Init_FW --- */
613 /* init_cb_t *init_cb; */
614 uint16_t firmware_options;
615 uint8_t alias[32];
616 uint8_t name_string[256];
617 uint8_t heartbeat_interval;
618
619 /* --- From FlashSysInfo --- */
620 uint8_t my_mac[MAC_ADDR_LEN];
621 uint8_t serial_number[16];
622 uint16_t port_num;
623 /* --- From GetFwState --- */
624 uint32_t firmware_state;
625 uint32_t addl_fw_state;
626
627 /* Linux kernel thread */
628 struct workqueue_struct *dpc_thread;
629 struct work_struct dpc_work;
630
631 /* Linux timer thread */
632 struct timer_list timer;
633 uint32_t timer_active;
634
635 /* Recovery Timers */
636 atomic_t check_relogin_timeouts;
637 uint32_t retry_reset_ha_cnt;
638 uint32_t isp_reset_timer; /* reset test timer */
639 uint32_t nic_reset_timer; /* simulated nic reset test timer */
640 int eh_start;
641 struct list_head free_srb_q;
642 uint16_t free_srb_q_count;
643 uint16_t num_srbs_allocated;
644
645 /* DMA Memory Block */
646 void *queues;
647 dma_addr_t queues_dma;
648 unsigned long queues_len;
649
650 #define MEM_ALIGN_VALUE \
651 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
652 sizeof(struct queue_entry))
653 /* request and response queue variables */
654 dma_addr_t request_dma;
655 struct queue_entry *request_ring;
656 struct queue_entry *request_ptr;
657 dma_addr_t response_dma;
658 struct queue_entry *response_ring;
659 struct queue_entry *response_ptr;
660 dma_addr_t shadow_regs_dma;
661 struct shadow_regs *shadow_regs;
662 uint16_t request_in; /* Current indexes. */
663 uint16_t request_out;
664 uint16_t response_in;
665 uint16_t response_out;
666
667 /* aen queue variables */
668 uint16_t aen_q_count; /* Number of available aen_q entries */
669 uint16_t aen_in; /* Current indexes */
670 uint16_t aen_out;
671 struct aen aen_q[MAX_AEN_ENTRIES];
672
673 struct ql4_aen_log aen_log;/* tracks all aens */
674
675 /* This mutex protects several threads to do mailbox commands
676 * concurrently.
677 */
678 struct mutex mbox_sem;
679
680 /* temporary mailbox status registers */
681 volatile uint8_t mbox_status_count;
682 volatile uint32_t mbox_status[MBOX_REG_COUNT];
683
684 /* FW ddb index map */
685 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
686
687 /* Saved srb for status continuation entry processing */
688 struct srb *status_srb;
689
690 uint8_t acb_version;
691
692 /* qla82xx specific fields */
693 struct device_reg_82xx __iomem *qla4_82xx_reg; /* Base I/O address */
694 unsigned long nx_pcibase; /* Base I/O address */
695 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
696 unsigned long nx_db_wr_ptr; /* Door bell write pointer */
697 unsigned long first_page_group_start;
698 unsigned long first_page_group_end;
699
700 uint32_t crb_win;
701 uint32_t curr_window;
702 uint32_t ddr_mn_window;
703 unsigned long mn_win_crb;
704 unsigned long ms_win_crb;
705 int qdr_sn_window;
706 rwlock_t hw_lock;
707 uint16_t func_num;
708 int link_width;
709
710 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
711 u32 nx_crb_mask;
712
713 uint8_t revision_id;
714 uint32_t fw_heartbeat_counter;
715
716 struct isp_operations *isp_ops;
717 struct ql82xx_hw_data hw;
718
719 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
720
721 uint32_t nx_dev_init_timeout;
722 uint32_t nx_reset_timeout;
723 void *fw_dump;
724 uint32_t fw_dump_size;
725 uint32_t fw_dump_capture_mask;
726 void *fw_dump_tmplt_hdr;
727 uint32_t fw_dump_tmplt_size;
728
729 struct completion mbx_intr_comp;
730
731 struct ipaddress_config ip_config;
732 struct iscsi_iface *iface_ipv4;
733 struct iscsi_iface *iface_ipv6_0;
734 struct iscsi_iface *iface_ipv6_1;
735
736 /* --- From About Firmware --- */
737 uint16_t iscsi_major;
738 uint16_t iscsi_minor;
739 uint16_t bootload_major;
740 uint16_t bootload_minor;
741 uint16_t bootload_patch;
742 uint16_t bootload_build;
743 uint16_t def_timeout; /* Default login timeout */
744
745 uint32_t flash_state;
746 #define QLFLASH_WAITING 0
747 #define QLFLASH_READING 1
748 #define QLFLASH_WRITING 2
749 struct dma_pool *chap_dma_pool;
750 uint8_t *chap_list; /* CHAP table cache */
751 struct mutex chap_sem;
752
753 #define CHAP_DMA_BLOCK_SIZE 512
754 struct workqueue_struct *task_wq;
755 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
756 #define SYSFS_FLAG_FW_SEL_BOOT 2
757 struct iscsi_boot_kset *boot_kset;
758 struct ql4_boot_tgt_info boot_tgt;
759 uint16_t phy_port_num;
760 uint16_t phy_port_cnt;
761 uint16_t iscsi_pci_func_cnt;
762 uint8_t model_name[16];
763 struct completion disable_acb_comp;
764 struct dma_pool *fw_ddb_dma_pool;
765 #define DDB_DMA_BLOCK_SIZE 512
766 uint16_t pri_ddb_idx;
767 uint16_t sec_ddb_idx;
768 int is_reset;
769 uint16_t temperature;
770
771 /* event work list */
772 struct list_head work_list;
773 spinlock_t work_lock;
774
775 /* mbox iocb */
776 #define MAX_MRB 128
777 struct mrb *active_mrb_array[MAX_MRB];
778 uint32_t mrb_index;
779
780 uint32_t *reg_tbl;
781 struct qla4_83xx_reset_template reset_tmplt;
782 struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address
783 for ISP8324 */
784 uint32_t pf_bit;
785 struct qla4_83xx_idc_information idc_info;
786 };
787
788 struct ql4_task_data {
789 struct scsi_qla_host *ha;
790 uint8_t iocb_req_cnt;
791 dma_addr_t data_dma;
792 void *req_buffer;
793 dma_addr_t req_dma;
794 uint32_t req_len;
795 void *resp_buffer;
796 dma_addr_t resp_dma;
797 uint32_t resp_len;
798 struct iscsi_task *task;
799 struct passthru_status sts;
800 struct work_struct task_work;
801 };
802
803 struct qla_endpoint {
804 struct Scsi_Host *host;
805 struct sockaddr_storage dst_addr;
806 };
807
808 struct qla_conn {
809 struct qla_endpoint *qla_ep;
810 };
811
is_ipv4_enabled(struct scsi_qla_host * ha)812 static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
813 {
814 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
815 }
816
is_ipv6_enabled(struct scsi_qla_host * ha)817 static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
818 {
819 return ((ha->ip_config.ipv6_options &
820 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
821 }
822
is_qla4010(struct scsi_qla_host * ha)823 static inline int is_qla4010(struct scsi_qla_host *ha)
824 {
825 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
826 }
827
is_qla4022(struct scsi_qla_host * ha)828 static inline int is_qla4022(struct scsi_qla_host *ha)
829 {
830 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
831 }
832
is_qla4032(struct scsi_qla_host * ha)833 static inline int is_qla4032(struct scsi_qla_host *ha)
834 {
835 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
836 }
837
is_qla40XX(struct scsi_qla_host * ha)838 static inline int is_qla40XX(struct scsi_qla_host *ha)
839 {
840 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
841 }
842
is_qla8022(struct scsi_qla_host * ha)843 static inline int is_qla8022(struct scsi_qla_host *ha)
844 {
845 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
846 }
847
is_qla8032(struct scsi_qla_host * ha)848 static inline int is_qla8032(struct scsi_qla_host *ha)
849 {
850 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324;
851 }
852
is_qla80XX(struct scsi_qla_host * ha)853 static inline int is_qla80XX(struct scsi_qla_host *ha)
854 {
855 return is_qla8022(ha) || is_qla8032(ha);
856 }
857
is_aer_supported(struct scsi_qla_host * ha)858 static inline int is_aer_supported(struct scsi_qla_host *ha)
859 {
860 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) ||
861 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324));
862 }
863
adapter_up(struct scsi_qla_host * ha)864 static inline int adapter_up(struct scsi_qla_host *ha)
865 {
866 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
867 (test_bit(AF_LINK_UP, &ha->flags) != 0) &&
868 (!test_bit(AF_LOOPBACK, &ha->flags));
869 }
870
to_qla_host(struct Scsi_Host * shost)871 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
872 {
873 return (struct scsi_qla_host *)iscsi_host_priv(shost);
874 }
875
isp_semaphore(struct scsi_qla_host * ha)876 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
877 {
878 return (is_qla4010(ha) ?
879 &ha->reg->u1.isp4010.nvram :
880 &ha->reg->u1.isp4022.semaphore);
881 }
882
isp_nvram(struct scsi_qla_host * ha)883 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
884 {
885 return (is_qla4010(ha) ?
886 &ha->reg->u1.isp4010.nvram :
887 &ha->reg->u1.isp4022.nvram);
888 }
889
isp_ext_hw_conf(struct scsi_qla_host * ha)890 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
891 {
892 return (is_qla4010(ha) ?
893 &ha->reg->u2.isp4010.ext_hw_conf :
894 &ha->reg->u2.isp4022.p0.ext_hw_conf);
895 }
896
isp_port_status(struct scsi_qla_host * ha)897 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
898 {
899 return (is_qla4010(ha) ?
900 &ha->reg->u2.isp4010.port_status :
901 &ha->reg->u2.isp4022.p0.port_status);
902 }
903
isp_port_ctrl(struct scsi_qla_host * ha)904 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
905 {
906 return (is_qla4010(ha) ?
907 &ha->reg->u2.isp4010.port_ctrl :
908 &ha->reg->u2.isp4022.p0.port_ctrl);
909 }
910
isp_port_error_status(struct scsi_qla_host * ha)911 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
912 {
913 return (is_qla4010(ha) ?
914 &ha->reg->u2.isp4010.port_err_status :
915 &ha->reg->u2.isp4022.p0.port_err_status);
916 }
917
isp_gp_out(struct scsi_qla_host * ha)918 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
919 {
920 return (is_qla4010(ha) ?
921 &ha->reg->u2.isp4010.gp_out :
922 &ha->reg->u2.isp4022.p0.gp_out);
923 }
924
eeprom_ext_hw_conf_offset(struct scsi_qla_host * ha)925 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
926 {
927 return (is_qla4010(ha) ?
928 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
929 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
930 }
931
932 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
933 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
934 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
935
ql4xxx_lock_flash(struct scsi_qla_host * a)936 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
937 {
938 if (is_qla4010(a))
939 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
940 QL4010_FLASH_SEM_BITS);
941 else
942 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
943 (QL4022_RESOURCE_BITS_BASE_CODE |
944 (a->mac_index)) << 13);
945 }
946
ql4xxx_unlock_flash(struct scsi_qla_host * a)947 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
948 {
949 if (is_qla4010(a))
950 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
951 else
952 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
953 }
954
ql4xxx_lock_nvram(struct scsi_qla_host * a)955 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
956 {
957 if (is_qla4010(a))
958 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
959 QL4010_NVRAM_SEM_BITS);
960 else
961 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
962 (QL4022_RESOURCE_BITS_BASE_CODE |
963 (a->mac_index)) << 10);
964 }
965
ql4xxx_unlock_nvram(struct scsi_qla_host * a)966 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
967 {
968 if (is_qla4010(a))
969 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
970 else
971 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
972 }
973
ql4xxx_lock_drvr(struct scsi_qla_host * a)974 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
975 {
976 if (is_qla4010(a))
977 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
978 QL4010_DRVR_SEM_BITS);
979 else
980 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
981 (QL4022_RESOURCE_BITS_BASE_CODE |
982 (a->mac_index)) << 1);
983 }
984
ql4xxx_unlock_drvr(struct scsi_qla_host * a)985 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
986 {
987 if (is_qla4010(a))
988 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
989 else
990 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
991 }
992
ql4xxx_reset_active(struct scsi_qla_host * ha)993 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
994 {
995 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
996 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
997 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
998 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
999 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
1000 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
1001
1002 }
1003
qla4_8xxx_rd_direct(struct scsi_qla_host * ha,const uint32_t crb_reg)1004 static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
1005 const uint32_t crb_reg)
1006 {
1007 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
1008 }
1009
qla4_8xxx_wr_direct(struct scsi_qla_host * ha,const uint32_t crb_reg,const uint32_t value)1010 static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
1011 const uint32_t crb_reg,
1012 const uint32_t value)
1013 {
1014 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
1015 }
1016
1017 /*---------------------------------------------------------------------------*/
1018
1019 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
1020
1021 #define INIT_ADAPTER 0
1022 #define RESET_ADAPTER 1
1023
1024 #define PRESERVE_DDB_LIST 0
1025 #define REBUILD_DDB_LIST 1
1026
1027 /* Defines for process_aen() */
1028 #define PROCESS_ALL_AENS 0
1029 #define FLUSH_DDB_CHANGED_AENS 1
1030
1031 /* Defines for udev events */
1032 #define QL4_UEVENT_CODE_FW_DUMP 0
1033
1034 #endif /*_QLA4XXX_H */
1035