Searched refs:AR_WA_D3_L1_DISABLE (Results 1 – 4 of 4) sorted by relevance
273 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) in ar9002_hw_configpcipowersave()274 val |= AR_WA_D3_L1_DISABLE; in ar9002_hw_configpcipowersave()279 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || in ar9002_hw_configpcipowersave()281 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { in ar9002_hw_configpcipowersave()282 val |= AR_WA_D3_L1_DISABLE; in ar9002_hw_configpcipowersave()305 val &= (~AR_WA_D3_L1_DISABLE); in ar9002_hw_configpcipowersave()312 val &= (~AR_WA_D3_L1_DISABLE); in ar9002_hw_configpcipowersave()321 val &= (~AR_WA_D3_L1_DISABLE); in ar9002_hw_configpcipowersave()
320 clr = AR_WA_UNTIE_RESET_EN | AR_WA_D3_L1_DISABLE; in ath9k_hw_wow_enable()335 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) in ath9k_hw_wow_enable()336 set |= AR_WA_D3_L1_DISABLE; in ath9k_hw_wow_enable()
581 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | in __ath9k_hw_init()590 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; in __ath9k_hw_init()2099 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_sleep()2143 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_network_sleep()
698 #define AR_WA_D3_L1_DISABLE (1 << 14) macro