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Searched refs:B43_PHY_OFDM (Results 1 – 10 of 10) sorted by relevance

/drivers/net/wireless/b43/
Dphy_lp.h93 #define B43_LPPHY_VERSION B43_PHY_OFDM(0x00) /* Version */
94 #define B43_LPPHY_BBCONFIG B43_PHY_OFDM(0x01) /* BBConfig */
95 #define B43_LPPHY_RX_STAT0 B43_PHY_OFDM(0x04) /* RX Status0 */
96 #define B43_LPPHY_RX_STAT1 B43_PHY_OFDM(0x05) /* RX Status1 */
97 #define B43_LPPHY_TX_ERROR B43_PHY_OFDM(0x07) /* TX Error */
98 #define B43_LPPHY_CHANNEL B43_PHY_OFDM(0x08) /* Channel */
99 #define B43_LPPHY_WORKAROUND B43_PHY_OFDM(0x09) /* workaround */
100 #define B43_LPPHY_FOURWIRE_ADDR B43_PHY_OFDM(0x0B) /* Fourwire Address */
101 #define B43_LPPHY_FOURWIREDATAHI B43_PHY_OFDM(0x0C) /* FourwireDataHi */
102 #define B43_LPPHY_FOURWIREDATALO B43_PHY_OFDM(0x0D) /* FourwireDataLo */
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Dphy_a.h8 #define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
9 #define B43_PHY_BBANDCFG B43_PHY_OFDM(0x01) /* Baseband config */
12 #define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */
13 #define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */
14 #define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */
15 #define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */
16 #define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */
17 #define B43_PHY_CRS0 B43_PHY_OFDM(0x29)
19 #define B43_PHY_PEAK_COUNT B43_PHY_OFDM(0x30)
20 #define B43_PHY_ANTDWELL B43_PHY_OFDM(0x2B) /* Antenna dwell */
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Dphy_lcn.h7 #define B43_PHY_LCN_AFE_CTL1 B43_PHY_OFDM(0x03B)
8 #define B43_PHY_LCN_AFE_CTL2 B43_PHY_OFDM(0x03C)
9 #define B43_PHY_LCN_RF_CTL1 B43_PHY_OFDM(0x04C)
10 #define B43_PHY_LCN_RF_CTL2 B43_PHY_OFDM(0x04D)
11 #define B43_PHY_LCN_TABLE_ADDR B43_PHY_OFDM(0x055) /* Table address */
12 #define B43_PHY_LCN_TABLE_DATALO B43_PHY_OFDM(0x056) /* Table data low */
13 #define B43_PHY_LCN_TABLE_DATAHI B43_PHY_OFDM(0x057) /* Table data high */
14 #define B43_PHY_LCN_RF_CTL3 B43_PHY_OFDM(0x0B0)
15 #define B43_PHY_LCN_RF_CTL4 B43_PHY_OFDM(0x0B1)
16 #define B43_PHY_LCN_RF_CTL5 B43_PHY_OFDM(0x0B7)
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Dwa.c46 b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x3800); in b43_wa_auxclipthr()
321 b43_phy_write(dev, B43_PHY_OFDM(0xC9), 0x0080); in b43_wa_crs_ed()
333 b43_phy_write(dev, B43_PHY_OFDM(0x2C), 0x005A); in b43_wa_crs_blank()
386 b43_phy_maskset(dev, B43_PHY_OFDM(0x1A), ~0x007F, 0x000F); in b43_wa_altagc()
387 b43_phy_maskset(dev, B43_PHY_OFDM(0x1A), ~0x3F80, 0x2B80); in b43_wa_altagc()
397 b43_phy_maskset(dev, B43_PHY_OFDM(0x88), ~0x00FF, 0x001C); in b43_wa_altagc()
398 b43_phy_maskset(dev, B43_PHY_OFDM(0x88), ~0x3F00, 0x0200); in b43_wa_altagc()
399 b43_phy_maskset(dev, B43_PHY_OFDM(0x96), ~0x00FF, 0x001C); in b43_wa_altagc()
400 b43_phy_maskset(dev, B43_PHY_OFDM(0x89), ~0x00FF, 0x0020); in b43_wa_altagc()
401 b43_phy_maskset(dev, B43_PHY_OFDM(0x89), ~0x3F00, 0x0200); in b43_wa_altagc()
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Dphy_a.c218 b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000); in b43_phy_ww()
219 b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300); in b43_phy_ww()
223 b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5); in b43_phy_ww()
242 b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80); in b43_phy_ww()
243 b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00); in b43_phy_ww()
244 b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0); in b43_phy_ww()
245 b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0); in b43_phy_ww()
246 b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF); in b43_phy_ww()
247 b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053); in b43_phy_ww()
249 b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000); in b43_phy_ww()
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Dphy_lp.c361 B43_PHY_OFDM(0xC1), in lpphy_save_dig_flt_state()
362 B43_PHY_OFDM(0xC2), in lpphy_save_dig_flt_state()
363 B43_PHY_OFDM(0xC3), in lpphy_save_dig_flt_state()
364 B43_PHY_OFDM(0xC4), in lpphy_save_dig_flt_state()
365 B43_PHY_OFDM(0xC5), in lpphy_save_dig_flt_state()
366 B43_PHY_OFDM(0xC6), in lpphy_save_dig_flt_state()
367 B43_PHY_OFDM(0xC7), in lpphy_save_dig_flt_state()
368 B43_PHY_OFDM(0xC8), in lpphy_save_dig_flt_state()
369 B43_PHY_OFDM(0xCF), in lpphy_save_dig_flt_state()
390 B43_PHY_OFDM(0xC1), in lpphy_restore_dig_flt_state()
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Dphy_ht.h67 #define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E)
68 #define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E)
69 #define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E)
Dphy_ht.c926 b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46); in b43_phy_ht_op_init()
937 b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd); in b43_phy_ht_op_init()
938 b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd); in b43_phy_ht_op_init()
939 b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd); in b43_phy_ht_op_init()
Dphy_common.h30 #define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY) macro
Dphy_g.c2020 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816); in b43_phy_initg()
2021 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006); in b43_phy_initg()
2024 b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00); in b43_phy_initg()
2028 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78); in b43_phy_initg()
2031 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4); in b43_phy_initg()
2092 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF); in b43_phy_initg()