Searched refs:BIT10 (Results 1 – 16 of 16) sorted by relevance
48 #define BIT10 0x00000400 macro163 #define WLAN_GET_FC_MOREFRAG(n) ((((unsigned short)(n) << 8) & (BIT10)) >> 10)184 #define WLAN_GET_CAP_INFO_SHORTSLOTTIME(n) ((((n)) & BIT10) >> 10)196 #define WLAN_GET_FC_MOREFRAG(n) ((((unsigned short)(n)) & (BIT10)) >> 10)217 #define WLAN_GET_CAP_INFO_SHORTSLOTTIME(n) (((n) & BIT10) >> 10)
46 #define WLAN_RATE_48M BIT10
42 #define BIT10 0x00000400 macro160 #define WLAN_GET_FC_MOREFRAG(n) ((((u16)(n) << 8) & (BIT10)) >> 10)182 #define WLAN_GET_CAP_INFO_SHORTSLOTTIME(n) ((((n)) & BIT10) >> 10)194 #define WLAN_GET_FC_MOREFRAG(n) ((((u16)(n)) & (BIT10)) >> 10)215 #define WLAN_GET_CAP_INFO_SHORTSLOTTIME(n) (((n) & BIT10) >> 10)
44 #define WLAN_RATE_48M BIT10
232 #define IMR_RXCMDOK BIT10255 #define TPPoll_StopBE BIT10385 #define RRSR_48M BIT10
181 #define BIT10 0x00000400 macro216 #define SRB_STATUS BIT10
65 #define BIT10 0x00000400 macro
317 #define RRSR_48M BIT10
61 #define BIT10 0x00000400 macro108 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
14 #define BIT10 0x00000400 macro
34 #define BIT10 0x00000400 macro
416 #define IRQ_RXDATA BIT102142 if (count == info->rbuf_fill_level || (reg & BIT10)) { in isr_rxdata()4321 case HDLC_ENCODING_NRZB: val |= BIT10; break; in sync_mode()4323 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()4325 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4327 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4394 case HDLC_ENCODING_NRZB: val |= BIT10; break; in sync_mode()4396 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()4398 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4400 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
563 #define MISCSTATUS_RI BIT10585 #define SICR_RI_INACTIVE BIT10586 #define SICR_RI (BIT11+BIT10)1707 else if ( (DmaVector&(BIT10|BIT9)) == BIT10) in mgsl_interrupt()4776 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()4851 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()4975 RegValue |= BIT10; in usc_set_sdlc_mode()5176 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break; in usc_set_sdlc_mode()5178 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break; in usc_set_sdlc_mode()
393 #define RRSR_48M BIT10
681 #define LPFC_SLI4_INTR10 BIT10
295 #define IRQ_CTS BIT10 // CTS status change