/drivers/scsi/ |
D | tmscsim.h | 188 #define BIT3 0x00000008 macro 197 #define UNIT_RETRY BIT3 209 #define SRB_MSGIN BIT3 226 #define UNDER_RUN BIT3 281 #define WIDE_NEGO_DONE BIT3 /* Not used ;-) */ 336 #define SEND_START_ BIT3 343 #define ACTIVE_NEGATION BIT3 393 #define GROUP_CODE_VALID BIT3 402 #define SUCCESSFUL_OP BIT3 408 #define SYNC_OFFSET_FLAG BIT3 [all …]
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D | dc395x.h | 72 #define BIT3 0x00000008 macro 81 #define UNIT_RETRY BIT3 131 #define UNDER_RUN BIT3 176 #define WIDE_NEGO_DONE BIT3 632 #define ACTIVE_NEGATION BIT3
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/drivers/staging/vt6655/ |
D | 80211hdr.h | 41 #define BIT3 0x00000008 macro 159 #define WLAN_GET_FC_FTYPE(n) ((((unsigned short)(n) >> 8) & (BIT2 | BIT3)) >> 2) 171 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3)) 172 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n) >> 8) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4) 178 #define WLAN_GET_CAP_INFO_CFPOLLREQ(n) ((((n) >> 8) & BIT3) >> 3) 192 #define WLAN_GET_FC_FTYPE(n) ((((unsigned short)(n)) & (BIT2 | BIT3)) >> 2) 204 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n)) & (BIT0|BIT1|BIT2|BIT3)) 205 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4) 211 #define WLAN_GET_CAP_INFO_CFPOLLREQ(n) (((n) & BIT3) >> 3)
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D | hostap.h | 39 #define WLAN_RATE_11M BIT3
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D | bssdb.h | 58 #define WLAN_STA_TIM BIT3
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D | ioctl.c | 522 if (sStartAPCmd.byBasicRate & BIT3) { in private_ioctl()
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/drivers/staging/vt6656/ |
D | 80211hdr.h | 35 #define BIT3 0x00000008 macro 155 #define WLAN_GET_FC_FTYPE(n) ((((u16)(n) >> 8) & (BIT2 | BIT3)) >> 2) 168 #define WLAN_GET_SEQ_FRGNUM(n) (((u16)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3)) 170 & (~(BIT0|BIT1|BIT2|BIT3))) >> 4) 176 #define WLAN_GET_CAP_INFO_CFPOLLREQ(n) ((((n) >> 8) & BIT3) >> 3) 190 #define WLAN_GET_FC_FTYPE(n) ((((u16)(n)) & (BIT2 | BIT3)) >> 2) 202 #define WLAN_GET_SEQ_FRGNUM(n) (((u16)(n)) & (BIT0|BIT1|BIT2|BIT3)) 203 #define WLAN_GET_SEQ_SEQNUM(n) ((((u16)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4) 209 #define WLAN_GET_CAP_INFO_CFPOLLREQ(n) (((n) & BIT3) >> 3)
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D | hostap.h | 37 #define WLAN_RATE_11M BIT3
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D | bssdb.h | 57 #define WLAN_STA_TIM BIT3
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/drivers/staging/rtl8192e/rtl8192e/ |
D | r8192E_hw.h | 144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \ 160 #define RCR_AB BIT3 218 #define SCR_RxDecEnable BIT3 239 #define IMR_BEDOK BIT3 248 #define TPPoll_VOQ BIT3 288 #define AcmHw_VoqEn BIT3 378 #define RRSR_11M BIT3
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/drivers/staging/rtl8192u/ |
D | r8192U_hw.h | 157 #define RCR_AB BIT3 // Accept broadcast packet 186 #define SCR_RxDecEnable BIT3 //Enable Rx Decryption 232 #define AcmHw_VoqEn BIT3 310 #define RRSR_11M BIT3
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D | r8192U.h | 54 #define BIT3 0x00000008 macro 101 #define COMP_RECV BIT3 // Receive data path.
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/drivers/video/via/ |
D | dvi.c | 359 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0() 384 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low() 391 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low() 470 viafb_write_reg_mask(CRD2, VIACR, 0, BIT3); in viafb_dvi_enable()
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D | lcd.c | 434 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3); in load_lcd_scaling() 446 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3); in load_lcd_scaling() 534 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew() 631 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3); in integrated_lvds_disable() 679 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); in integrated_lvds_enable() 773 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3); in viafb_lcd_enable() 774 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3); in viafb_lcd_enable()
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D | share.h | 31 #define BIT3 0x08 macro
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/drivers/staging/rtl8192u/ieee80211/ |
D | rtl819x_Qos.h | 7 #define BIT3 0x00000008 macro 387 #define GET_BE_UAPSD(_apsd) ((_apsd) & BIT3) 388 #define SET_BE_UAPSD(_apsd) ((_apsd) |= BIT3)
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/drivers/staging/rtl8192e/ |
D | rtl819x_Qos.h | 27 #define BIT3 0x00000008 macro 282 #define GET_BE_UAPSD(_apsd) ((_apsd) & BIT3) 283 #define SET_BE_UAPSD(_apsd) ((_apsd) |= BIT3)
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/drivers/char/pcmcia/ |
D | synclink_cs.c | 314 #define PVR_AUTOCTS BIT3 682 #define CMD_TXFIFO BIT3 // release current tx FIFO 1192 if (gis & (BIT3 + BIT2)) in mgslpc_isr() 3122 val |= BIT3; in hdlc_mode() 3131 val |= BIT4 + BIT3; in hdlc_mode() 3262 set_reg_bits(info, CHA + PVR, BIT3); in hdlc_mode() 3264 clear_reg_bits(info, CHA + PVR, BIT3); in hdlc_mode() 3299 clear_reg_bits(info, CHA + MODE, BIT3); in rx_stop() 3316 set_reg_bits(info, CHA + MODE, BIT3); in rx_start() 3532 val |= BIT3; in async_mode() [all …]
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/drivers/staging/keucr/ |
D | smilecc.c | 45 #define BIT3 0x08 macro
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/drivers/tty/ |
D | synclink.c | 493 #define TRANSMIT_STATUS BIT3 510 #define RXSTATUS_CRC_ERROR BIT3 511 #define RXSTATUS_FRAMING_ERROR BIT3 550 #define TXSTATUS_CRC_SENT BIT3 570 #define MISCSTATUS_RCC_UNDERRUN BIT3 596 #define SICR_RCC_UNDERFLOW BIT3 630 #define TXSTATUS_CRC_SENT BIT3 1452 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 )); in mgsl_isr_receive_data() 1610 if ( status & BIT3 ) { in mgsl_isr_receive_dma() 5063 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3)); in usc_set_sdlc_mode() [all …]
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D | synclinkmp.c | 425 #define CCTS BIT3 441 #define OVRN BIT3 1540 RegValue |= BIT3; in set_break() 1542 RegValue &= ~BIT3; in set_break() 2590 if (status & BIT3 << shift) in synclinkmp_interrupt() 2599 if (dmastatus & BIT3 << shift) in synclinkmp_interrupt() 4421 case 6: RegValue |= BIT5 + BIT3; break; in async_mode() 4422 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; in async_mode() 4596 RegValue |= BIT3; in hdlc_mode() 4758 if (!(status & BIT3)) in get_signals() [all …]
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D | synclink_gt.c | 2013 if (status & BIT3) { in dsr_change() 2258 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma() 2747 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); in rx_enable() 4182 val |= BIT3; in async_mode() 4264 val |= BIT3; in async_mode() 4439 val |= BIT3; /* 010, rxclk = BRG */ in sync_mode() 4552 if (status & BIT3) in get_signals() 4594 val |= BIT3; in msc_set_vcr() 4611 val |= BIT3; in set_signals() 4613 val &= ~BIT3; in set_signals()
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/drivers/staging/rtl8187se/ |
D | r8185b_init.c | 212 u1bTmp &= ~BIT3; in HwHSSIThreeWire() 1206 TmpU1b = TmpU1b & ~BIT3; in rtl8185b_adapter_start() 1216 write_nic_byte(dev, PSR, (btPSR | BIT3)); in rtl8185b_adapter_start()
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D | r8180_hw.h | 27 #define BIT3 0x00000008 macro
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/drivers/net/wireless/rtlwifi/rtl8192de/ |
D | reg.h | 386 #define RRSR_11M BIT3 521 #define WOW_UWF BIT3 /* Unicast Wakeup frame. */
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