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Searched refs:CRTC (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/nouveau/dispnv04/
Dcrtc.c52 crtcstate->CRTC[index]); in crtc_wr_cio_state()
61 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; in nv_crtc_set_digital_vibrance()
63 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
64 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; in nv_crtc_set_digital_vibrance()
346 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; in nv_crtc_mode_set_vga()
347 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; in nv_crtc_mode_set_vga()
348 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; in nv_crtc_mode_set_vga()
349 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | in nv_crtc_mode_set_vga()
351 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; in nv_crtc_mode_set_vga()
352 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | in nv_crtc_mode_set_vga()
[all …]
Dcursor.c34 crtcstate->CRTC[index]); in crtc_wr_cio_state()
45 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = in nv04_cursor_set_offset()
48 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = in nv04_cursor_set_offset()
51 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= in nv04_cursor_set_offset()
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; in nv04_cursor_set_offset()
Dtvnv04.c108 state->CRTC[NV_CIO_CRE_49] |= 0x10; in nv04_tv_bind()
110 state->CRTC[NV_CIO_CRE_49] &= ~0x10; in nv04_tv_bind()
113 state->CRTC[NV_CIO_CRE_LCD__INDEX]); in nv04_tv_bind()
115 state->CRTC[NV_CIO_CRE_49]); in nv04_tv_bind()
Ddfp.c109 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &= in nv04_dfp_disable()
251 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX]; in nv04_dfp_prepare()
252 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX]; in nv04_dfp_prepare()
Ddisp.h20 uint8_t CRTC[0xa0]; member
Dtvnv17.c416 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ in nv17_tv_prepare()
482 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */ in nv17_tv_mode_set()
483 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */ in nv17_tv_mode_set()
Dhw.h377 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; in nv_show_cursor()
Dhw.c378 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); in rd_cio_state()
385 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); in wr_cio_state()
/drivers/video/matrox/
Dmatroxfb_misc.c303 hw->CRTC[0] = ht-4; in matroxfb_vgaHWinit()
304 hw->CRTC[1] = hd; in matroxfb_vgaHWinit()
305 hw->CRTC[2] = hd; in matroxfb_vgaHWinit()
306 hw->CRTC[3] = (hbe & 0x1F) | 0x80; in matroxfb_vgaHWinit()
307 hw->CRTC[4] = hs; in matroxfb_vgaHWinit()
308 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F); in matroxfb_vgaHWinit()
309 hw->CRTC[6] = vt & 0xFF; in matroxfb_vgaHWinit()
310 hw->CRTC[7] = ((vt & 0x100) >> 8) | in matroxfb_vgaHWinit()
318 hw->CRTC[8] = 0x00; in matroxfb_vgaHWinit()
319 hw->CRTC[9] = ((vd & 0x200) >> 4) | in matroxfb_vgaHWinit()
[all …]
Dmatroxfb_base.c326 p0 = minfo->hw.CRTC[0x0D] = pos & 0xFF; in matrox_pan_var()
327 p1 = minfo->hw.CRTC[0x0C] = (pos & 0xFF00) >> 8; in matrox_pan_var()
820 hw->CRTC[0x0D] = pos & 0xFF; in matroxfb_set_par()
821 hw->CRTC[0x0C] = (pos & 0xFF00) >> 8; in matroxfb_set_par()
Dmatroxfb_base.h290 unsigned char CRTC[25]; member
/drivers/video/
Dneofb.c289 par->CRTC[0] = htotal - 5; in vgaHWInit()
290 par->CRTC[1] = (var->xres >> 3) - 1; in vgaHWInit()
291 par->CRTC[2] = (var->xres >> 3) - 1; in vgaHWInit()
292 par->CRTC[3] = ((htotal - 1) & 0x1F) | 0x80; in vgaHWInit()
293 par->CRTC[4] = ((var->xres + var->right_margin) >> 3); in vgaHWInit()
294 par->CRTC[5] = (((htotal - 1) & 0x20) << 2) in vgaHWInit()
296 par->CRTC[6] = (vtotal - 2) & 0xFF; in vgaHWInit()
297 par->CRTC[7] = (((vtotal - 2) & 0x100) >> 8) in vgaHWInit()
304 par->CRTC[8] = 0x00; in vgaHWInit()
305 par->CRTC[9] = (((var->yres - 1) & 0x200) >> 4) | 0x40; in vgaHWInit()
[all …]
DKconfig1292 G450/G550 hardware can display TV picture only from secondary CRTC,
/drivers/video/savage/
Dsavagefb_driver.c132 VGAwCR(17, reg->CRTC[17] & ~0x80, par); in vgaHWRestore()
135 VGAwCR(i, reg->CRTC[i], par); in vgaHWRestore()
173 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; in vgaHWInit()
174 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; in vgaHWInit()
175 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; in vgaHWInit()
176 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; in vgaHWInit()
177 reg->CRTC[0x04] = (timings->HSyncStart >> 3); in vgaHWInit()
178 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | in vgaHWInit()
180 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; in vgaHWInit()
181 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | in vgaHWInit()
[all …]
Dsavagefb.h155 unsigned char CRTC[25]; /* Crtc Controller */ member
/drivers/usb/misc/sisusbvga/
Dsisusb_struct.h73 unsigned char CRTC[0x19]; member
Dsisusb_init.c390 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i]; in SiS_SetCRTCRegs()
/drivers/staging/imx-drm/
DTODO13 - Add KMS plane support for CRTC driver
/drivers/video/sis/
Dvstruct.h136 unsigned char CRTC[0x19]; member
Dinit.c1894 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i]; in SiS_SetCRTCRegs()
1901 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i]; in SiS_SetCRTCRegs()
Dinit301.c3025 tempax = SiS_Pr->SiS_StandTable[index].CRTC[0]; in SiS_GetRAMDAC2DATA()
3026 tempbx = SiS_Pr->SiS_StandTable[index].CRTC[6]; in SiS_GetRAMDAC2DATA()
3027 temp1 = SiS_Pr->SiS_StandTable[index].CRTC[7]; in SiS_GetRAMDAC2DATA()
/drivers/gpu/drm/
DKconfig36 FB and CRTC helpers for KMS drivers.
/drivers/staging/xgifb/
Dvb_setmode.c91 CRTCdata = XGI330_StandTable.CRTC[i]; in XGI_SetCRTCRegs()