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Searched refs:DISPLAY_PLANE_ENABLE (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/gma500/
Dmdfld_intel_display.c272 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_disable_crtc()
274 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_disable_crtc()
384 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in mdfld_crtc_dpms()
386 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
412 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
428 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
460 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_crtc_dpms()
462 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
882 dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE; in mdfld_crtc_mode_set()
Doaktrail_crtc.c208 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_dpms()
210 temp | DISPLAY_PLANE_ENABLE); in oaktrail_crtc_dpms()
230 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_dpms()
232 temp & ~DISPLAY_PLANE_ENABLE); in oaktrail_crtc_dpms()
Doaktrail_hdmi.c364 dspcntr |= DISPLAY_PLANE_ENABLE; in oaktrail_crtc_hdmi_mode_set()
398 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_hdmi_dpms()
399 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()
466 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_hdmi_dpms()
467 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()
Dpsb_intel_display.c357 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in psb_intel_crtc_dpms()
359 temp | DISPLAY_PLANE_ENABLE); in psb_intel_crtc_dpms()
380 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in psb_intel_crtc_dpms()
382 temp & ~DISPLAY_PLANE_ENABLE); in psb_intel_crtc_dpms()
581 dspcntr |= DISPLAY_PLANE_ENABLE; in psb_intel_crtc_mode_set()
Dcdv_intel_display.c908 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in cdv_intel_crtc_dpms()
910 temp | DISPLAY_PLANE_ENABLE); in cdv_intel_crtc_dpms()
967 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in cdv_intel_crtc_dpms()
969 temp & ~DISPLAY_PLANE_ENABLE); in cdv_intel_crtc_dpms()
1180 dspcntr |= DISPLAY_PLANE_ENABLE; in cdv_intel_crtc_mode_set()
Dmdfld_device.c357 PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, map->cntr); in mdfld_restore_display_registers()
Dpsb_intel_reg.h636 #define DISPLAY_PLANE_ENABLE (1 << 31) macro
/drivers/gpu/drm/i915/
Dintel_sprite.c512 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); in intel_enable_primary()
526 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); in intel_disable_primary()
Dintel_display.c1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE); in assert_plane()
1273 WARN((val & DISPLAY_PLANE_ENABLE), in assert_planes_disabled()
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, in assert_planes_disabled()
1941 if (val & DISPLAY_PLANE_ENABLE) in intel_enable_plane()
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); in intel_enable_plane()
1965 if ((val & DISPLAY_PLANE_ENABLE) == 0) in intel_disable_plane()
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); in intel_disable_plane()
5824 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE); in haswell_crtc_mode_set()
9150 if ((val & DISPLAY_PLANE_ENABLE) && in intel_check_plane_mapping()
Dintel_tv.c1096 I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE); in intel_tv_mode_set()
Di915_reg.h3055 #define DISPLAY_PLANE_ENABLE (1<<31) macro