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Searched refs:DPLL_VGA_MODE_DIS (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/gma500/
Dcdv_intel_display.c271 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); in cdv_dpll_set_clock_cdv()
1120 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
1183 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
Doaktrail_crtc.c437 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set()
Dpsb_intel_reg.h244 #define DPLL_VGA_MODE_DIS (1 << 28) macro
Dpsb_intel_display.c532 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
/drivers/gpu/drm/i915/
Dintel_display.c4251 dpll = DPLL_VGA_MODE_DIS; in vlv_update_pll()
4351 dpll = DPLL_VGA_MODE_DIS; in i9xx_update_pll()
4458 dpll = DPLL_VGA_MODE_DIS; in i8xx_update_pll()
Di915_reg.h954 #define DPLL_VGA_MODE_DIS (1 << 28) macro