Searched refs:DP_TP_CTL (Results 1 – 3 of 3) sorted by relevance
200 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()243 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()258 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()261 I915_WRITE(DP_TP_CTL(PORT_E), temp); in hsw_fdi_link_train()262 POSTING_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()1289 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_post_disable()1292 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_post_disable()1408 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { in intel_ddi_prepare_link_retrain()1416 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_prepare_link_retrain()1419 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_prepare_link_retrain()[all …]
1707 uint32_t temp = I915_READ(DP_TP_CTL(port)); in intel_dp_set_link_train()1730 I915_WRITE(DP_TP_CTL(port), temp); in intel_dp_set_link_train()1803 val = I915_READ(DP_TP_CTL(port)); in intel_dp_set_idle_link_train()1806 I915_WRITE(DP_TP_CTL(port), val); in intel_dp_set_idle_link_train()
4612 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) macro