Searched refs:DP_TP_CTL_LINK_TRAIN_PAT1 (Results 1 – 3 of 3) sorted by relevance
203 DP_TP_CTL_LINK_TRAIN_PAT1 | in hsw_fdi_link_train()260 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; in hsw_fdi_link_train()1291 val |= DP_TP_CTL_LINK_TRAIN_PAT1; in intel_ddi_post_disable()1418 val |= DP_TP_CTL_LINK_TRAIN_PAT1; in intel_ddi_prepare_link_retrain()1427 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; in intel_ddi_prepare_link_retrain()
1721 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; in intel_dp_set_link_train()
4619 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) macro