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Searched refs:DSPCNTR (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_pm.c3717 I915_WRITE(DSPCNTR(pipe), in gen6_init_clock_gating()
3718 I915_READ(DSPCNTR(pipe)) | in gen6_init_clock_gating()
3793 I915_WRITE(DSPCNTR(pipe), in haswell_init_clock_gating()
3794 I915_READ(DSPCNTR(pipe)) | in haswell_init_clock_gating()
3897 I915_WRITE(DSPCNTR(pipe), in ivybridge_init_clock_gating()
3898 I915_READ(DSPCNTR(pipe)) | in ivybridge_init_clock_gating()
4005 I915_WRITE(DSPCNTR(pipe), in valleyview_init_clock_gating()
4006 I915_READ(DSPCNTR(pipe)) | in valleyview_init_clock_gating()
Dintel_sprite.c504 int reg = DSPCNTR(intel_crtc->plane); in intel_enable_primary()
521 int reg = DSPCNTR(intel_crtc->plane); in intel_disable_primary()
Dintel_display.c1251 reg = DSPCNTR(plane); in assert_plane()
1271 reg = DSPCNTR(pipe); in assert_planes_disabled()
1281 reg = DSPCNTR(i); in assert_planes_disabled()
1939 reg = DSPCNTR(plane); in intel_enable_plane()
1963 reg = DSPCNTR(plane); in intel_disable_plane()
2106 reg = DSPCNTR(plane); in i9xx_update_plane()
2203 reg = DSPCNTR(plane); in ironlake_update_plane()
4750 I915_WRITE(DSPCNTR(plane), dspcntr); in i9xx_crtc_mode_set()
4751 POSTING_READ(DSPCNTR(plane)); in i9xx_crtc_mode_set()
5722 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); in ironlake_crtc_mode_set()
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Dintel_tv.c1090 int dspcntr_reg = DSPCNTR(intel_crtc->plane); in intel_tv_mode_set()
Di915_reg.h3097 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) macro