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Searched refs:EN0_ISR (Results 1 – 9 of 9) sorted by relevance

/drivers/net/ethernet/8390/
Dlib8390.c265 isr = ei_inb(e8390_base+EN0_ISR); in __ei_tx_timeout()
440 ei_inb_p(e8390_base + EN0_ISR), in __ei_interrupt()
450 ei_inb_p(e8390_base + EN0_ISR)); in __ei_interrupt()
453 while ((interrupts = ei_inb_p(e8390_base + EN0_ISR)) != 0 && in __ei_interrupt()
458 ei_outb_p(interrupts, e8390_base + EN0_ISR); in __ei_interrupt()
478 ei_outb_p(ENISR_COUNTERS, e8390_base + EN0_ISR); /* Ack intr. */ in __ei_interrupt()
483 ei_outb_p(ENISR_RDC, e8390_base + EN0_ISR); in __ei_interrupt()
495 ei_outb_p(ENISR_ALL, e8390_base + EN0_ISR); /* Ack. most intrs. */ in __ei_interrupt()
498 ei_outb_p(0xff, e8390_base + EN0_ISR); /* Ack. all intrs. */ in __ei_interrupt()
551 ei_outb_p(ENISR_TX_ERR, e8390_base + EN0_ISR); /* Ack intr. */ in ei_tx_err()
[all …]
Dne2k-pci.c295 while ((inb(ioaddr + EN0_ISR) & ENISR_RESET) == 0) in ne2k_pci_init_one()
303 outb(0xff, ioaddr + EN0_ISR); /* Ack all intr. */ in ne2k_pci_init_one()
317 {0xFF, EN0_ISR}, in ne2k_pci_init_one()
465 while ((inb(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) in ne2k_pci_reset_8390()
470 outb(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */ in ne2k_pci_reset_8390()
505 outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne2k_pci_get_8390_hdr()
557 outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne2k_pci_block_input()
597 outb(ENISR_RDC, nic_base + EN0_ISR); in ne2k_pci_block_output()
622 while ((inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) in ne2k_pci_block_output()
630 outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne2k_pci_block_output()
Daxnet_cs.c203 {0xFF, EN0_ISR}, in get_prom()
478 outb_p(0xFF, nic_base + EN0_ISR); /* Clear bogus intr. */ in axnet_open()
533 if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0) in axnet_reset_8390()
537 outb_p(ENISR_RESET, nic_base + EN0_ISR); /* Ack intr. */ in axnet_reset_8390()
565 if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) { in ei_watchdog()
925 isr = inb(e8390_base+EN0_ISR); in axnet_tx_timeout()
1121 inb_p(e8390_base + EN0_ISR), in ax_interrupt()
1130 inb_p(e8390_base + EN0_ISR)); in ax_interrupt()
1132 outb_p(0x00, e8390_base + EN0_ISR); in ax_interrupt()
1136 while ((interrupts = inb_p(e8390_base + EN0_ISR)) != 0 && in ax_interrupt()
[all …]
Dne.c343 while ((inb_p(ioaddr + EN0_ISR) & ENISR_RESET) == 0) in ne_probe1()
355 outb_p(0xff, ioaddr + EN0_ISR); /* Ack all intr. */ in ne_probe1()
370 {0xFF, EN0_ISR}, in ne_probe1()
570 while ((inb_p(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) in ne_reset_8390()
575 outb_p(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */ in ne_reset_8390()
609 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne_get_8390_hdr()
682 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne_block_input()
733 outb_p(ENISR_RDC, nic_base + EN0_ISR); in ne_block_output()
777 while ((inb_p(nic_base + EN0_ISR) & ENISR_RDC) == 0) in ne_block_output()
785 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ne_block_output()
Dne-h8300.c265 {0xFF, EN0_ISR}, in ne_probe1()
385 while ((inb_p(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) in ne_reset_8390()
390 outb_p(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */ in ne_reset_8390()
426 outb_p(ENISR_RDC, NE_BASE + EN0_ISR); /* Ack intr. */ in ne_get_8390_hdr()
502 outb_p(ENISR_RDC, NE_BASE + EN0_ISR); /* Ack intr. */ in ne_block_input()
553 outb_p(ENISR_RDC, NE_BASE + EN0_ISR); in ne_block_output()
600 while ((inb_p(NE_BASE + EN0_ISR) & ENISR_RDC) == 0) in ne_block_output()
608 outb_p(ENISR_RDC, NE_BASE + EN0_ISR); /* Ack intr. */ in ne_block_output()
Dpcnet_cs.c337 {0xFF, EN0_ISR}, in get_prom()
910 outb_p(0xFF, nic_base + EN0_ISR); /* Clear bogus intr. */ in pcnet_open()
966 if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0) in pcnet_reset_8390()
970 outb_p(ENISR_RESET, nic_base + EN0_ISR); /* Ack intr. */ in pcnet_reset_8390()
1023 if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) { in ei_watchdog()
1150 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in dma_get_8390_hdr()
1203 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in dma_block_input()
1243 outb_p(ENISR_RDC, nic_base + EN0_ISR); in dma_block_output()
1278 while ((inb_p(nic_base + EN0_ISR) & ENISR_RDC) == 0) in dma_block_output()
1286 outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in dma_block_output()
Detherh.c348 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_block_output()
362 while ((readb (addr + EN0_ISR) & ENISR_RDC) == 0) in etherh_block_output()
371 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_block_output()
412 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_block_input()
449 writeb (ENISR_RDC, addr + EN0_ISR); in etherh_get_header()
Dax88796.c159 while ((ei_inb(addr + EN0_ISR) & ENISR_RESET) == 0) { in ax_reset_8390()
166 ei_outb(ENISR_RESET, addr + EN0_ISR); /* Ack intr. */ in ax_reset_8390()
200 ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ax_get_8390_hdr()
279 ei_outb(ENISR_RDC, nic_base + EN0_ISR); in ax_block_output()
295 while ((ei_inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) { in ax_block_output()
304 ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */ in ax_block_output()
D8390.h172 #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ macro