Searched refs:ENISR_RESET (Results 1 – 10 of 10) sorted by relevance
99 while ((z_readb(NE_BASE + NE_EN0_ISR) & ENISR_RESET) == 0) in zorro8390_reset_8390()104 z_writeb(ENISR_RESET, NE_BASE + NE_EN0_ISR); /* Ack intr */ in zorro8390_reset_8390()307 while ((z_readb(ioaddr + NE_EN0_ISR) & ENISR_RESET) == 0) in zorro8390_init()
218 while ((inb(ioaddr + NE_EN0_ISR) & ENISR_RESET) == 0) in apne_probe1()366 while ((inb(NE_BASE+NE_EN0_ISR) & ENISR_RESET) == 0) in apne_reset_8390()371 outb(ENISR_RESET, NE_BASE + NE_EN0_ISR); /* Ack intr. */ in apne_reset_8390()
295 while ((inb(ioaddr + EN0_ISR) & ENISR_RESET) == 0) in ne2k_pci_init_one()465 while ((inb(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) in ne2k_pci_reset_8390()470 outb(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */ in ne2k_pci_reset_8390()
343 while ((inb_p(ioaddr + EN0_ISR) & ENISR_RESET) == 0) in ne_probe1()570 while ((inb_p(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) in ne_reset_8390()575 outb_p(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */ in ne_reset_8390()
166 while ((ei_inb(addr + NE_EN0_ISR) & ENISR_RESET) == 0) { in mcf8390_reset_8390()173 ei_outb(ENISR_RESET, addr + NE_EN0_ISR); in mcf8390_reset_8390()
196 #define ENISR_RESET 0x80 /* Reset completed */ macro
385 while ((inb_p(NE_BASE+EN0_ISR) & ENISR_RESET) == 0) in ne_reset_8390()390 outb_p(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */ in ne_reset_8390()
159 while ((ei_inb(addr + EN0_ISR) & ENISR_RESET) == 0) { in ax_reset_8390()166 ei_outb(ENISR_RESET, addr + EN0_ISR); /* Ack intr. */ in ax_reset_8390()
533 if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0) in axnet_reset_8390()537 outb_p(ENISR_RESET, nic_base + EN0_ISR); /* Ack intr. */ in axnet_reset_8390()
966 if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0) in pcnet_reset_8390()970 outb_p(ENISR_RESET, nic_base + EN0_ISR); /* Ack intr. */ in pcnet_reset_8390()