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Searched refs:FLD_MOD (Results 1 – 8 of 8) sorted by relevance

/drivers/video/omap2/dss/
Dti_hdmi_4xxx_ip.c101 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ in hdmi_pll_init()
102 r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */ in hdmi_pll_init()
108 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ in hdmi_pll_init()
109 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ in hdmi_pll_init()
110 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ in hdmi_pll_init()
111 r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */ in hdmi_pll_init()
116 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ in hdmi_pll_init()
118 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ in hdmi_pll_init()
124 r = FLD_MOD(r, fmt->regm2, 24, 18); in hdmi_pll_init()
125 r = FLD_MOD(r, fmt->regmf, 17, 0); in hdmi_pll_init()
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Ddsi.c112 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
1504 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ in dsi_pll_set_clock_div()
1506 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); in dsi_pll_set_clock_div()
1508 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); in dsi_pll_set_clock_div()
1510 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, in dsi_pll_set_clock_div()
1513 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, in dsi_pll_set_clock_div()
1528 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ in dsi_pll_set_clock_div()
1532 l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */ in dsi_pll_set_clock_div()
1535 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ in dsi_pll_set_clock_div()
1536 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ in dsi_pll_set_clock_div()
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Ddss.c62 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
180 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ in dss_sdi_init()
181 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ in dss_sdi_init()
182 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ in dss_sdi_init()
186 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ in dss_sdi_init()
187 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ in dss_sdi_init()
188 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ in dss_sdi_init()
Drfbi.c70 rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
336 l = FLD_MOD(l, 1, 0, 0); /* enable */ in rfbi_transfer_area()
338 l = FLD_MOD(l, 1, 4, 4); /* ITE */ in rfbi_transfer_area()
762 l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */ in rfbi_configure()
763 l = FLD_MOD(l, 0, 1, 1); /* clear bypass */ in rfbi_configure()
Ddispc.c59 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
954 val = FLD_MOD(val, chan, shift, shift); in dispc_ovl_set_channel_out()
955 val = FLD_MOD(val, chan2, 31, 30); in dispc_ovl_set_channel_out()
957 val = FLD_MOD(val, channel, shift, shift); in dispc_ovl_set_channel_out()
1087 val = FLD_MOD(val, enable, 9, 9); in dispc_ovl_set_vid_color_conv()
1150 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ in dispc_init_fifos()
1151 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ in dispc_init_fifos()
1152 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ in dispc_init_fifos()
1153 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ in dispc_init_fifos()
2614 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ in dispc_wb_setup()
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Dti_hdmi_4xxx_ip.h178 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
Ddss.h73 #define FLD_MOD(orig, val, start, end) \ macro
/drivers/gpu/drm/gma500/
Dmdfld_dsi_output.h47 #define FLD_MOD(orig, val, start, end) \ macro
51 REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end))