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Searched refs:FW_BLC_SELF (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/gma500/
Dcdv_intel_display.c728 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_intel_disable_self_refresh()
731 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_intel_disable_self_refresh()
732 REG_READ(FW_BLC_SELF); in cdv_intel_disable_self_refresh()
786 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in cdv_intel_update_watermark()
787 REG_READ(FW_BLC_SELF); in cdv_intel_update_watermark()
Dpsb_intel_reg.h610 #define FW_BLC_SELF 0x20e0 macro
/drivers/gpu/drm/i915/
Dintel_pm.c1378 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in g4x_update_wm()
1380 I915_WRITE(FW_BLC_SELF, in g4x_update_wm()
1381 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); in g4x_update_wm()
1450 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in i965_update_wm()
1454 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) in i965_update_wm()
1527 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); in i9xx_update_wm()
1554 I915_WRITE(FW_BLC_SELF, in i9xx_update_wm()
1557 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); in i9xx_update_wm()
1576 I915_WRITE(FW_BLC_SELF, in i9xx_update_wm()
Di915_debugfs.c1303 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; in i915_sr_status()
Dintel_display.c3677 u32 fw_bcl_self = I915_READ(FW_BLC_SELF); in g4x_fixup_plane()
3679 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); in g4x_fixup_plane()
3684 I915_WRITE(FW_BLC_SELF, fw_bcl_self); in g4x_fixup_plane()
Di915_reg.h623 #define FW_BLC_SELF 0x020e0 /* 915+ only */ macro