1 /*
2 include/comedi.h (installed as /usr/include/comedi.h)
3 header file for comedi
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU Lesser General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 */
23
24 #ifndef _COMEDI_H
25 #define _COMEDI_H
26
27 #define COMEDI_MAJORVERSION 0
28 #define COMEDI_MINORVERSION 7
29 #define COMEDI_MICROVERSION 76
30 #define VERSION "0.7.76"
31
32 /* comedi's major device number */
33 #define COMEDI_MAJOR 98
34
35 /*
36 maximum number of minor devices. This can be increased, although
37 kernel structures are currently statically allocated, thus you
38 don't want this to be much more than you actually use.
39 */
40 #define COMEDI_NDEVICES 16
41
42 /* number of config options in the config structure */
43 #define COMEDI_NDEVCONFOPTS 32
44
45 /*
46 * NOTE: 'comedi_config --init-data' is deprecated
47 *
48 * The following indexes in the config options were used by
49 * comedi_config to pass firmware blobs from user space to the
50 * comedi drivers. The request_firmware() hotplug interface is
51 * now used by all comedi drivers instead.
52 */
53
54 /* length of nth chunk of firmware data -*/
55 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH 25
56 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH 26
57 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH 27
58 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH 28
59 /* most significant 32 bits of pointer address (if needed) */
60 #define COMEDI_DEVCONF_AUX_DATA_HI 29
61 /* least significant 32 bits of pointer address */
62 #define COMEDI_DEVCONF_AUX_DATA_LO 30
63 #define COMEDI_DEVCONF_AUX_DATA_LENGTH 31 /* total data length */
64
65 /* max length of device and driver names */
66 #define COMEDI_NAMELEN 20
67
68 /* packs and unpacks a channel/range number */
69
70 #define CR_PACK(chan, rng, aref) \
71 ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan))
72 #define CR_PACK_FLAGS(chan, range, aref, flags) \
73 (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
74
75 #define CR_CHAN(a) ((a)&0xffff)
76 #define CR_RANGE(a) (((a)>>16)&0xff)
77 #define CR_AREF(a) (((a)>>24)&0x03)
78
79 #define CR_FLAGS_MASK 0xfc000000
80 #define CR_ALT_FILTER (1<<26)
81 #define CR_DITHER CR_ALT_FILTER
82 #define CR_DEGLITCH CR_ALT_FILTER
83 #define CR_ALT_SOURCE (1<<27)
84 #define CR_EDGE (1<<30)
85 #define CR_INVERT (1<<31)
86
87 #define AREF_GROUND 0x00 /* analog ref = analog ground */
88 #define AREF_COMMON 0x01 /* analog ref = analog common */
89 #define AREF_DIFF 0x02 /* analog ref = differential */
90 #define AREF_OTHER 0x03 /* analog ref = other (undefined) */
91
92 /* counters -- these are arbitrary values */
93 #define GPCT_RESET 0x0001
94 #define GPCT_SET_SOURCE 0x0002
95 #define GPCT_SET_GATE 0x0004
96 #define GPCT_SET_DIRECTION 0x0008
97 #define GPCT_SET_OPERATION 0x0010
98 #define GPCT_ARM 0x0020
99 #define GPCT_DISARM 0x0040
100 #define GPCT_GET_INT_CLK_FRQ 0x0080
101
102 #define GPCT_INT_CLOCK 0x0001
103 #define GPCT_EXT_PIN 0x0002
104 #define GPCT_NO_GATE 0x0004
105 #define GPCT_UP 0x0008
106 #define GPCT_DOWN 0x0010
107 #define GPCT_HWUD 0x0020
108 #define GPCT_SIMPLE_EVENT 0x0040
109 #define GPCT_SINGLE_PERIOD 0x0080
110 #define GPCT_SINGLE_PW 0x0100
111 #define GPCT_CONT_PULSE_OUT 0x0200
112 #define GPCT_SINGLE_PULSE_OUT 0x0400
113
114 /* instructions */
115
116 #define INSN_MASK_WRITE 0x8000000
117 #define INSN_MASK_READ 0x4000000
118 #define INSN_MASK_SPECIAL 0x2000000
119
120 #define INSN_READ (0 | INSN_MASK_READ)
121 #define INSN_WRITE (1 | INSN_MASK_WRITE)
122 #define INSN_BITS (2 | INSN_MASK_READ|INSN_MASK_WRITE)
123 #define INSN_CONFIG (3 | INSN_MASK_READ|INSN_MASK_WRITE)
124 #define INSN_GTOD (4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
125 #define INSN_WAIT (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
126 #define INSN_INTTRIG (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
127
128 /* trigger flags */
129 /* These flags are used in comedi_trig structures */
130
131 #define TRIG_BOGUS 0x0001 /* do the motions */
132 #define TRIG_DITHER 0x0002 /* enable dithering */
133 #define TRIG_DEGLITCH 0x0004 /* enable deglitching */
134 /*#define TRIG_RT 0x0008 *//* perform op in real time */
135 #define TRIG_CONFIG 0x0010 /* perform configuration, not triggering */
136 #define TRIG_WAKE_EOS 0x0020 /* wake up on end-of-scan events */
137 /*#define TRIG_WRITE 0x0040*//* write to bidirectional devices */
138
139 /* command flags */
140 /* These flags are used in comedi_cmd structures */
141
142 /* try to use a real-time interrupt while performing command */
143 #define CMDF_PRIORITY 0x00000008
144
145 #define TRIG_RT CMDF_PRIORITY /* compatibility definition */
146
147 #define CMDF_WRITE 0x00000040
148 #define TRIG_WRITE CMDF_WRITE /* compatibility definition */
149
150 #define CMDF_RAWDATA 0x00000080
151
152 #define COMEDI_EV_START 0x00040000
153 #define COMEDI_EV_SCAN_BEGIN 0x00080000
154 #define COMEDI_EV_CONVERT 0x00100000
155 #define COMEDI_EV_SCAN_END 0x00200000
156 #define COMEDI_EV_STOP 0x00400000
157
158 #define TRIG_ROUND_MASK 0x00030000
159 #define TRIG_ROUND_NEAREST 0x00000000
160 #define TRIG_ROUND_DOWN 0x00010000
161 #define TRIG_ROUND_UP 0x00020000
162 #define TRIG_ROUND_UP_NEXT 0x00030000
163
164 /* trigger sources */
165
166 #define TRIG_ANY 0xffffffff
167 #define TRIG_INVALID 0x00000000
168
169 #define TRIG_NONE 0x00000001 /* never trigger */
170 #define TRIG_NOW 0x00000002 /* trigger now + N ns */
171 #define TRIG_FOLLOW 0x00000004 /* trigger on next lower level trig */
172 #define TRIG_TIME 0x00000008 /* trigger at time N ns */
173 #define TRIG_TIMER 0x00000010 /* trigger at rate N ns */
174 #define TRIG_COUNT 0x00000020 /* trigger when count reaches N */
175 #define TRIG_EXT 0x00000040 /* trigger on external signal N */
176 #define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */
177 #define TRIG_OTHER 0x00000100 /* driver defined */
178
179 /* subdevice flags */
180
181 #define SDF_BUSY 0x0001 /* device is busy */
182 #define SDF_BUSY_OWNER 0x0002 /* device is busy with your job */
183 #define SDF_LOCKED 0x0004 /* subdevice is locked */
184 #define SDF_LOCK_OWNER 0x0008 /* you own lock */
185 #define SDF_MAXDATA 0x0010 /* maxdata depends on channel */
186 #define SDF_FLAGS 0x0020 /* flags depend on channel */
187 #define SDF_RANGETYPE 0x0040 /* range type depends on channel */
188 #define SDF_MODE0 0x0080 /* can do mode 0 */
189 #define SDF_MODE1 0x0100 /* can do mode 1 */
190 #define SDF_MODE2 0x0200 /* can do mode 2 */
191 #define SDF_MODE3 0x0400 /* can do mode 3 */
192 #define SDF_MODE4 0x0800 /* can do mode 4 */
193 #define SDF_CMD 0x1000 /* can do commands (deprecated) */
194 #define SDF_SOFT_CALIBRATED 0x2000 /* subdevice uses software calibration */
195 #define SDF_CMD_WRITE 0x4000 /* can do output commands */
196 #define SDF_CMD_READ 0x8000 /* can do input commands */
197
198 /* subdevice can be read (e.g. analog input) */
199 #define SDF_READABLE 0x00010000
200 /* subdevice can be written (e.g. analog output) */
201 #define SDF_WRITABLE 0x00020000
202 #define SDF_WRITEABLE SDF_WRITABLE /* spelling error in API */
203 /* subdevice does not have externally visible lines */
204 #define SDF_INTERNAL 0x00040000
205 #define SDF_GROUND 0x00100000 /* can do aref=ground */
206 #define SDF_COMMON 0x00200000 /* can do aref=common */
207 #define SDF_DIFF 0x00400000 /* can do aref=diff */
208 #define SDF_OTHER 0x00800000 /* can do aref=other */
209 #define SDF_DITHER 0x01000000 /* can do dithering */
210 #define SDF_DEGLITCH 0x02000000 /* can do deglitching */
211 #define SDF_MMAP 0x04000000 /* can do mmap() */
212 #define SDF_RUNNING 0x08000000 /* subdevice is acquiring data */
213 #define SDF_LSAMPL 0x10000000 /* subdevice uses 32-bit samples */
214 #define SDF_PACKED 0x20000000 /* subdevice can do packed DIO */
215 /* re recyle these flags for PWM */
216 #define SDF_PWM_COUNTER SDF_MODE0 /* PWM can automatically switch off */
217 #define SDF_PWM_HBRIDGE SDF_MODE1 /* PWM is signed (H-bridge) */
218
219 /* subdevice types */
220
221 enum comedi_subdevice_type {
222 COMEDI_SUBD_UNUSED, /* unused by driver */
223 COMEDI_SUBD_AI, /* analog input */
224 COMEDI_SUBD_AO, /* analog output */
225 COMEDI_SUBD_DI, /* digital input */
226 COMEDI_SUBD_DO, /* digital output */
227 COMEDI_SUBD_DIO, /* digital input/output */
228 COMEDI_SUBD_COUNTER, /* counter */
229 COMEDI_SUBD_TIMER, /* timer */
230 COMEDI_SUBD_MEMORY, /* memory, EEPROM, DPRAM */
231 COMEDI_SUBD_CALIB, /* calibration DACs */
232 COMEDI_SUBD_PROC, /* processor, DSP */
233 COMEDI_SUBD_SERIAL, /* serial IO */
234 COMEDI_SUBD_PWM /* PWM */
235 };
236
237 /* configuration instructions */
238
239 enum configuration_ids {
240 INSN_CONFIG_DIO_INPUT = 0,
241 INSN_CONFIG_DIO_OUTPUT = 1,
242 INSN_CONFIG_DIO_OPENDRAIN = 2,
243 INSN_CONFIG_ANALOG_TRIG = 16,
244 /* INSN_CONFIG_WAVEFORM = 17, */
245 /* INSN_CONFIG_TRIG = 18, */
246 /* INSN_CONFIG_COUNTER = 19, */
247 INSN_CONFIG_ALT_SOURCE = 20,
248 INSN_CONFIG_DIGITAL_TRIG = 21,
249 INSN_CONFIG_BLOCK_SIZE = 22,
250 INSN_CONFIG_TIMER_1 = 23,
251 INSN_CONFIG_FILTER = 24,
252 INSN_CONFIG_CHANGE_NOTIFY = 25,
253
254 INSN_CONFIG_SERIAL_CLOCK = 26, /*ALPHA*/
255 INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
256 INSN_CONFIG_DIO_QUERY = 28,
257 INSN_CONFIG_PWM_OUTPUT = 29,
258 INSN_CONFIG_GET_PWM_OUTPUT = 30,
259 INSN_CONFIG_ARM = 31,
260 INSN_CONFIG_DISARM = 32,
261 INSN_CONFIG_GET_COUNTER_STATUS = 33,
262 INSN_CONFIG_RESET = 34,
263 /* Use CTR as single pulsegenerator */
264 INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001,
265 /* Use CTR as pulsetraingenerator */
266 INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002,
267 /* Use the counter as encoder */
268 INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003,
269 INSN_CONFIG_SET_GATE_SRC = 2001, /* Set gate source */
270 INSN_CONFIG_GET_GATE_SRC = 2002, /* Get gate source */
271 /* Set master clock source */
272 INSN_CONFIG_SET_CLOCK_SRC = 2003,
273 INSN_CONFIG_GET_CLOCK_SRC = 2004, /* Get master clock source */
274 INSN_CONFIG_SET_OTHER_SRC = 2005, /* Set other source */
275 /* INSN_CONFIG_GET_OTHER_SRC = 2006,*//* Get other source */
276 /* Get size in bytes of subdevice's on-board fifos used during
277 * streaming input/output */
278 INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006,
279 INSN_CONFIG_SET_COUNTER_MODE = 4097,
280 /* INSN_CONFIG_8254_SET_MODE is deprecated */
281 INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE,
282 INSN_CONFIG_8254_READ_STATUS = 4098,
283 INSN_CONFIG_SET_ROUTING = 4099,
284 INSN_CONFIG_GET_ROUTING = 4109,
285 /* PWM */
286 INSN_CONFIG_PWM_SET_PERIOD = 5000, /* sets frequency */
287 INSN_CONFIG_PWM_GET_PERIOD = 5001, /* gets frequency */
288 INSN_CONFIG_GET_PWM_STATUS = 5002, /* is it running? */
289 /* sets H bridge: duty cycle and sign bit for a relay at the
290 * same time */
291 INSN_CONFIG_PWM_SET_H_BRIDGE = 5003,
292 /* gets H bridge data: duty cycle and the sign bit */
293 INSN_CONFIG_PWM_GET_H_BRIDGE = 5004
294 };
295
296 /*
297 * Settings for INSN_CONFIG_DIGITAL_TRIG:
298 * data[0] = INSN_CONFIG_DIGITAL_TRIG
299 * data[1] = trigger ID
300 * data[2] = configuration operation
301 * data[3] = configuration parameter 1
302 * data[4] = configuration parameter 2
303 * data[5] = configuration parameter 3
304 *
305 * operation parameter 1 parameter 2 parameter 3
306 * --------------------------------- ----------- ----------- -----------
307 * COMEDI_DIGITAL_TRIG_DISABLE
308 * COMEDI_DIGITAL_TRIG_ENABLE_EDGES left-shift rising-edges falling-edges
309 * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS left-shift high-levels low-levels
310 *
311 * COMEDI_DIGITAL_TRIG_DISABLE returns the trigger to its default, inactive,
312 * unconfigured state.
313 *
314 * COMEDI_DIGITAL_TRIG_ENABLE_EDGES sets the rising and/or falling edge inputs
315 * that each can fire the trigger.
316 *
317 * COMEDI_DIGITAL_TRIG_ENABLE_LEVELS sets a combination of high and/or low
318 * level inputs that can fire the trigger.
319 *
320 * "left-shift" is useful if the trigger has more than 32 inputs to specify the
321 * first input for this configuration.
322 *
323 * Some sequences of INSN_CONFIG_DIGITAL_TRIG instructions may have a (partly)
324 * accumulative effect, depending on the low-level driver. This is useful
325 * when setting up a trigger that has more than 32 inputs or has a combination
326 * of edge and level triggered inputs.
327 */
328 enum comedi_digital_trig_op {
329 COMEDI_DIGITAL_TRIG_DISABLE = 0,
330 COMEDI_DIGITAL_TRIG_ENABLE_EDGES = 1,
331 COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = 2
332 };
333
334 enum comedi_io_direction {
335 COMEDI_INPUT = 0,
336 COMEDI_OUTPUT = 1,
337 COMEDI_OPENDRAIN = 2
338 };
339
340 enum comedi_support_level {
341 COMEDI_UNKNOWN_SUPPORT = 0,
342 COMEDI_SUPPORTED,
343 COMEDI_UNSUPPORTED
344 };
345
346 /* ioctls */
347
348 #define CIO 'd'
349 #define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig)
350 #define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo)
351 #define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo)
352 #define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo)
353 #define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig)
354 #define COMEDI_LOCK _IO(CIO, 5)
355 #define COMEDI_UNLOCK _IO(CIO, 6)
356 #define COMEDI_CANCEL _IO(CIO, 7)
357 #define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo)
358 #define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd)
359 #define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd)
360 #define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist)
361 #define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn)
362 #define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig)
363 #define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo)
364 #define COMEDI_POLL _IO(CIO, 15)
365
366 /* structures */
367
368 struct comedi_trig {
369 unsigned int subdev; /* subdevice */
370 unsigned int mode; /* mode */
371 unsigned int flags;
372 unsigned int n_chan; /* number of channels */
373 unsigned int *chanlist; /* channel/range list */
374 short *data; /* data list, size depends on subd flags */
375 unsigned int n; /* number of scans */
376 unsigned int trigsrc;
377 unsigned int trigvar;
378 unsigned int trigvar1;
379 unsigned int data_len;
380 unsigned int unused[3];
381 };
382
383 struct comedi_insn {
384 unsigned int insn;
385 unsigned int n;
386 unsigned int __user *data;
387 unsigned int subdev;
388 unsigned int chanspec;
389 unsigned int unused[3];
390 };
391
392 struct comedi_insnlist {
393 unsigned int n_insns;
394 struct comedi_insn __user *insns;
395 };
396
397 struct comedi_cmd {
398 unsigned int subdev;
399 unsigned int flags;
400
401 unsigned int start_src;
402 unsigned int start_arg;
403
404 unsigned int scan_begin_src;
405 unsigned int scan_begin_arg;
406
407 unsigned int convert_src;
408 unsigned int convert_arg;
409
410 unsigned int scan_end_src;
411 unsigned int scan_end_arg;
412
413 unsigned int stop_src;
414 unsigned int stop_arg;
415
416 unsigned int *chanlist; /* channel/range list */
417 unsigned int chanlist_len;
418
419 short __user *data; /* data list, size depends on subd flags */
420 unsigned int data_len;
421 };
422
423 struct comedi_chaninfo {
424 unsigned int subdev;
425 unsigned int __user *maxdata_list;
426 unsigned int __user *flaglist;
427 unsigned int __user *rangelist;
428 unsigned int unused[4];
429 };
430
431 struct comedi_rangeinfo {
432 unsigned int range_type;
433 void __user *range_ptr;
434 };
435
436 struct comedi_krange {
437 int min; /* fixed point, multiply by 1e-6 */
438 int max; /* fixed point, multiply by 1e-6 */
439 unsigned int flags;
440 };
441
442 struct comedi_subdinfo {
443 unsigned int type;
444 unsigned int n_chan;
445 unsigned int subd_flags;
446 unsigned int timer_type;
447 unsigned int len_chanlist;
448 unsigned int maxdata;
449 unsigned int flags; /* channel flags */
450 unsigned int range_type; /* lookup in kernel */
451 unsigned int settling_time_0;
452 /* see support_level enum for values */
453 unsigned insn_bits_support;
454 unsigned int unused[8];
455 };
456
457 struct comedi_devinfo {
458 unsigned int version_code;
459 unsigned int n_subdevs;
460 char driver_name[COMEDI_NAMELEN];
461 char board_name[COMEDI_NAMELEN];
462 int read_subdevice;
463 int write_subdevice;
464 int unused[30];
465 };
466
467 struct comedi_devconfig {
468 char board_name[COMEDI_NAMELEN];
469 int options[COMEDI_NDEVCONFOPTS];
470 };
471
472 struct comedi_bufconfig {
473 unsigned int subdevice;
474 unsigned int flags;
475
476 unsigned int maximum_size;
477 unsigned int size;
478
479 unsigned int unused[4];
480 };
481
482 struct comedi_bufinfo {
483 unsigned int subdevice;
484 unsigned int bytes_read;
485
486 unsigned int buf_write_ptr;
487 unsigned int buf_read_ptr;
488 unsigned int buf_write_count;
489 unsigned int buf_read_count;
490
491 unsigned int bytes_written;
492
493 unsigned int unused[4];
494 };
495
496 /* range stuff */
497
498 #define __RANGE(a, b) ((((a)&0xffff)<<16)|((b)&0xffff))
499
500 #define RANGE_OFFSET(a) (((a)>>16)&0xffff)
501 #define RANGE_LENGTH(b) ((b)&0xffff)
502
503 #define RF_UNIT(flags) ((flags)&0xff)
504 #define RF_EXTERNAL (1<<8)
505
506 #define UNIT_volt 0
507 #define UNIT_mA 1
508 #define UNIT_none 2
509
510 #define COMEDI_MIN_SPEED ((unsigned int)0xffffffff)
511
512 /* callback stuff */
513 /* only relevant to kernel modules. */
514
515 #define COMEDI_CB_EOS 1 /* end of scan */
516 #define COMEDI_CB_EOA 2 /* end of acquisition/output */
517 #define COMEDI_CB_BLOCK 4 /* data has arrived:
518 * wakes up read() / write() */
519 #define COMEDI_CB_EOBUF 8 /* DEPRECATED: end of buffer */
520 #define COMEDI_CB_ERROR 16 /* card error during acquisition */
521 #define COMEDI_CB_OVERFLOW 32 /* buffer overflow/underflow */
522
523 /**********************************************************/
524 /* everything after this line is ALPHA */
525 /**********************************************************/
526
527 /*
528 8254 specific configuration.
529
530 It supports two config commands:
531
532 0 ID: INSN_CONFIG_SET_COUNTER_MODE
533 1 8254 Mode
534 I8254_MODE0, I8254_MODE1, ..., I8254_MODE5
535 OR'ed with:
536 I8254_BCD, I8254_BINARY
537
538 0 ID: INSN_CONFIG_8254_READ_STATUS
539 1 <-- Status byte returned here.
540 B7 = Output
541 B6 = NULL Count
542 B5 - B0 Current mode.
543
544 */
545
546 enum i8254_mode {
547 I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
548 I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
549 I8254_MODE2 = (2 << 1), /* Rate generator */
550 I8254_MODE3 = (3 << 1), /* Square wave mode */
551 I8254_MODE4 = (4 << 1), /* Software triggered strobe */
552 I8254_MODE5 = (5 << 1), /* Hardware triggered strobe
553 * (retriggerable) */
554 I8254_BCD = 1, /* use binary-coded decimal instead of binary
555 * (pretty useless) */
556 I8254_BINARY = 0
557 };
558
NI_USUAL_PFI_SELECT(unsigned pfi_channel)559 static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel)
560 {
561 if (pfi_channel < 10)
562 return 0x1 + pfi_channel;
563 else
564 return 0xb + pfi_channel;
565 }
566
NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)567 static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)
568 {
569 if (rtsi_channel < 7)
570 return 0xb + rtsi_channel;
571 else
572 return 0x1b;
573 }
574
575 /* mode bits for NI general-purpose counters, set with
576 * INSN_CONFIG_SET_COUNTER_MODE */
577 #define NI_GPCT_COUNTING_MODE_SHIFT 16
578 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20
579 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
580 enum ni_gpct_mode_bits {
581 NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
582 NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
583 NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
584 NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
585 NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
586 NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
587 NI_GPCT_STOP_MODE_MASK = 0x60,
588 NI_GPCT_STOP_ON_GATE_BITS = 0x00,
589 NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
590 NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
591 NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
592 NI_GPCT_OUTPUT_MODE_MASK = 0x300,
593 NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
594 NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
595 NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
596 NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
597 NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
598 NI_GPCT_DISARM_AT_TC_BITS = 0x400,
599 NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
600 NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
601 NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
602 NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
603 NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
604 NI_GPCT_COUNTING_MODE_NORMAL_BITS =
605 0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
606 NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
607 0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
608 NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
609 0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
610 NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
611 0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
612 NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
613 0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
614 NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
615 0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
616 NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
617 NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
618 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
619 NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
620 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
621 NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
622 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
623 NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
624 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
625 NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
626 NI_GPCT_COUNTING_DIRECTION_MASK =
627 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
628 NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
629 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
630 NI_GPCT_COUNTING_DIRECTION_UP_BITS =
631 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
632 NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
633 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
634 NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
635 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
636 NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
637 NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
638 NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
639 NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
640 NI_GPCT_OR_GATE_BIT = 0x10000000,
641 NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
642 };
643
644 /* Bits for setting a clock source with
645 * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
646 enum ni_gpct_clock_source_bits {
647 NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
648 NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
649 NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
650 NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
651 NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
652 NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
653 NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
654 /* NI 660x-specific */
655 NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6,
656 NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
657 NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
658 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
659 NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
660 NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
661 /* divide source by 2 */
662 NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000,
663 /* divide source by 8 */
664 NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000,
665 NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
666 };
NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n)667 static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n)
668 {
669 /* NI 660x-specific */
670 return 0x10 + n;
671 }
NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)672 static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)
673 {
674 return 0x18 + n;
675 }
NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n)676 static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n)
677 {
678 /* no pfi on NI 660x */
679 return 0x20 + n;
680 }
681
682 /* Possibilities for setting a gate source with
683 INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
684 May be bitwise-or'd with CR_EDGE or CR_INVERT. */
685 enum ni_gpct_gate_select {
686 /* m-series gates */
687 NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
688 NI_GPCT_AI_START2_GATE_SELECT = 0x12,
689 NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
690 NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
691 NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
692 NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
693 NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
694 NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
695 /* more gates for 660x */
696 NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
697 NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
698 /* more gates for 660x "second gate" */
699 NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
700 NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
701 /* m-series "second gate" sources are unknown,
702 * we should add them here with an offset of 0x300 when
703 * known. */
704 NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
705 };
NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)706 static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
707 {
708 return 0x102 + n;
709 }
NI_GPCT_RTSI_GATE_SELECT(unsigned n)710 static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n)
711 {
712 return NI_USUAL_RTSI_SELECT(n);
713 }
NI_GPCT_PFI_GATE_SELECT(unsigned n)714 static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n)
715 {
716 return NI_USUAL_PFI_SELECT(n);
717 }
NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)718 static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)
719 {
720 return 0x202 + n;
721 }
722
723 /* Possibilities for setting a source with
724 INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
725 enum ni_gpct_other_index {
726 NI_GPCT_SOURCE_ENCODER_A,
727 NI_GPCT_SOURCE_ENCODER_B,
728 NI_GPCT_SOURCE_ENCODER_Z
729 };
730 enum ni_gpct_other_select {
731 /* m-series gates */
732 /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
733 NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
734 };
NI_GPCT_PFI_OTHER_SELECT(unsigned n)735 static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n)
736 {
737 return NI_USUAL_PFI_SELECT(n);
738 }
739
740 /* start sources for ni general-purpose counters for use with
741 INSN_CONFIG_ARM */
742 enum ni_gpct_arm_source {
743 NI_GPCT_ARM_IMMEDIATE = 0x0,
744 NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1, /* Start both the counter
745 * and the adjacent paired
746 * counter simultaneously */
747 /* NI doesn't document bits for selecting hardware arm triggers.
748 * If the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
749 * significant bits (3 bits for 660x or 5 bits for m-series)
750 * through to the hardware. This will at least allow someone to
751 * figure out what the bits do later. */
752 NI_GPCT_ARM_UNKNOWN = 0x1000,
753 };
754
755 /* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
756 enum ni_gpct_filter_select {
757 NI_GPCT_FILTER_OFF = 0x0,
758 NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
759 NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
760 NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
761 NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
762 NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
763 NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
764 };
765
766 /* PFI digital filtering options for ni m-series for use with
767 * INSN_CONFIG_FILTER. */
768 enum ni_pfi_filter_select {
769 NI_PFI_FILTER_OFF = 0x0,
770 NI_PFI_FILTER_125ns = 0x1,
771 NI_PFI_FILTER_6425ns = 0x2,
772 NI_PFI_FILTER_2550us = 0x3
773 };
774
775 /* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
776 enum ni_mio_clock_source {
777 NI_MIO_INTERNAL_CLOCK = 0,
778 NI_MIO_RTSI_CLOCK = 1, /* doesn't work for m-series, use
779 NI_MIO_PLL_RTSI_CLOCK() */
780 /* the NI_MIO_PLL_* sources are m-series only */
781 NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
782 NI_MIO_PLL_PXI10_CLOCK = 3,
783 NI_MIO_PLL_RTSI0_CLOCK = 4
784 };
NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)785 static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)
786 {
787 return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
788 }
789
790 /* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
791 The numbers assigned are not arbitrary, they correspond to the bits required
792 to program the board. */
793 enum ni_rtsi_routing {
794 NI_RTSI_OUTPUT_ADR_START1 = 0,
795 NI_RTSI_OUTPUT_ADR_START2 = 1,
796 NI_RTSI_OUTPUT_SCLKG = 2,
797 NI_RTSI_OUTPUT_DACUPDN = 3,
798 NI_RTSI_OUTPUT_DA_START1 = 4,
799 NI_RTSI_OUTPUT_G_SRC0 = 5,
800 NI_RTSI_OUTPUT_G_GATE0 = 6,
801 NI_RTSI_OUTPUT_RGOUT0 = 7,
802 NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
803 NI_RTSI_OUTPUT_RTSI_OSC = 12 /* pre-m-series always have RTSI
804 * clock on line 7 */
805 };
NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)806 static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
807 {
808 return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
809 }
810
811 /* Signals which can be routed to an NI PFI pin on an m-series board with
812 * INSN_CONFIG_SET_ROUTING. These numbers are also returned by
813 * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing
814 * cannot be changed. The numbers assigned are not arbitrary, they correspond
815 * to the bits required to program the board. */
816 enum ni_pfi_routing {
817 NI_PFI_OUTPUT_PFI_DEFAULT = 0,
818 NI_PFI_OUTPUT_AI_START1 = 1,
819 NI_PFI_OUTPUT_AI_START2 = 2,
820 NI_PFI_OUTPUT_AI_CONVERT = 3,
821 NI_PFI_OUTPUT_G_SRC1 = 4,
822 NI_PFI_OUTPUT_G_GATE1 = 5,
823 NI_PFI_OUTPUT_AO_UPDATE_N = 6,
824 NI_PFI_OUTPUT_AO_START1 = 7,
825 NI_PFI_OUTPUT_AI_START_PULSE = 8,
826 NI_PFI_OUTPUT_G_SRC0 = 9,
827 NI_PFI_OUTPUT_G_GATE0 = 10,
828 NI_PFI_OUTPUT_EXT_STROBE = 11,
829 NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
830 NI_PFI_OUTPUT_GOUT0 = 13,
831 NI_PFI_OUTPUT_GOUT1 = 14,
832 NI_PFI_OUTPUT_FREQ_OUT = 15,
833 NI_PFI_OUTPUT_PFI_DO = 16,
834 NI_PFI_OUTPUT_I_ATRIG = 17,
835 NI_PFI_OUTPUT_RTSI0 = 18,
836 NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
837 NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
838 NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
839 NI_PFI_OUTPUT_CDI_SAMPLE = 29,
840 NI_PFI_OUTPUT_CDO_UPDATE = 30
841 };
NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)842 static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
843 {
844 return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
845 }
846
847 /* Signals which can be routed to output on a NI PFI pin on a 660x board
848 with INSN_CONFIG_SET_ROUTING. The numbers assigned are
849 not arbitrary, they correspond to the bits required
850 to program the board. Lines 0 to 7 can only be set to
851 NI_660X_PFI_OUTPUT_DIO. Lines 32 to 39 can only be set to
852 NI_660X_PFI_OUTPUT_COUNTER. */
853 enum ni_660x_pfi_routing {
854 NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */
855 NI_660X_PFI_OUTPUT_DIO = 2, /* static digital output */
856 };
857
858 /* NI External Trigger lines. These values are not arbitrary, but are related
859 * to the bits required to program the board (offset by 1 for historical
860 * reasons). */
NI_EXT_PFI(unsigned pfi_channel)861 static inline unsigned NI_EXT_PFI(unsigned pfi_channel)
862 {
863 return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
864 }
NI_EXT_RTSI(unsigned rtsi_channel)865 static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel)
866 {
867 return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
868 }
869
870 /* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
871 enum comedi_counter_status_flags {
872 COMEDI_COUNTER_ARMED = 0x1,
873 COMEDI_COUNTER_COUNTING = 0x2,
874 COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
875 };
876
877 /* Clock sources for CDIO subdevice on NI m-series boards. Used as the
878 * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd
879 * with CR_INVERT to change polarity. */
880 enum ni_m_series_cdio_scan_begin_src {
881 NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
882 NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
883 NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
884 NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
885 NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
886 NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
887 NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
888 NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
889 NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
890 NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
891 };
NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)892 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
893 {
894 return NI_USUAL_PFI_SELECT(pfi_channel);
895 }
NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)896 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
897 {
898 return NI_USUAL_RTSI_SELECT(rtsi_channel);
899 }
900
901 /* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI
902 * boards. These scan begin sources can also be bitwise-or'd with CR_INVERT to
903 * change polarity. */
NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)904 static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
905 {
906 return NI_USUAL_PFI_SELECT(pfi_channel);
907 }
NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)908 static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
909 {
910 return NI_USUAL_RTSI_SELECT(rtsi_channel);
911 }
912
913 /* Bits for setting a clock source with
914 * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
915 enum ni_freq_out_clock_source_bits {
916 NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */
917 NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC /* 100 KHz */
918 };
919
920 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
921 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
922 enum amplc_dio_clock_source {
923 AMPLC_DIO_CLK_CLKN, /* per channel external clock
924 input/output pin (pin is only an
925 input when clock source set to this
926 value, otherwise it is an output) */
927 AMPLC_DIO_CLK_10MHZ, /* 10 MHz internal clock */
928 AMPLC_DIO_CLK_1MHZ, /* 1 MHz internal clock */
929 AMPLC_DIO_CLK_100KHZ, /* 100 kHz internal clock */
930 AMPLC_DIO_CLK_10KHZ, /* 10 kHz internal clock */
931 AMPLC_DIO_CLK_1KHZ, /* 1 kHz internal clock */
932 AMPLC_DIO_CLK_OUTNM1, /* output of preceding counter channel
933 (for channel 0, preceding counter
934 channel is channel 2 on preceding
935 counter subdevice, for first counter
936 subdevice, preceding counter
937 subdevice is the last counter
938 subdevice) */
939 AMPLC_DIO_CLK_EXT, /* per chip external input pin */
940 /* the following are "enhanced" clock sources for PCIe models */
941 AMPLC_DIO_CLK_VCC, /* clock input HIGH */
942 AMPLC_DIO_CLK_GND, /* clock input LOW */
943 AMPLC_DIO_CLK_PAT_PRESENT, /* "pattern present" signal */
944 AMPLC_DIO_CLK_20MHZ /* 20 MHz internal clock */
945 };
946
947 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
948 * timer subdevice on some Amplicon DIO PCIe boards (amplc_dio200 driver). */
949 enum amplc_dio_ts_clock_src {
950 AMPLC_DIO_TS_CLK_1GHZ, /* 1 ns period with 20 ns granularity */
951 AMPLC_DIO_TS_CLK_1MHZ, /* 1 us period */
952 AMPLC_DIO_TS_CLK_1KHZ /* 1 ms period */
953 };
954
955 /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
956 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
957 enum amplc_dio_gate_source {
958 AMPLC_DIO_GAT_VCC, /* internal high logic level */
959 AMPLC_DIO_GAT_GND, /* internal low logic level */
960 AMPLC_DIO_GAT_GATN, /* per channel external gate input */
961 AMPLC_DIO_GAT_NOUTNM2, /* negated output of counter channel
962 minus 2 (for channels 0 or 1,
963 channel minus 2 is channel 1 or 2 on
964 the preceding counter subdevice, for
965 the first counter subdevice the
966 preceding counter subdevice is the
967 last counter subdevice) */
968 AMPLC_DIO_GAT_RESERVED4,
969 AMPLC_DIO_GAT_RESERVED5,
970 AMPLC_DIO_GAT_RESERVED6,
971 AMPLC_DIO_GAT_RESERVED7,
972 /* the following are "enhanced" gate sources for PCIe models */
973 AMPLC_DIO_GAT_NGATN = 6, /* negated per channel gate input */
974 AMPLC_DIO_GAT_OUTNM2, /* non-negated output of counter
975 channel minus 2 */
976 AMPLC_DIO_GAT_PAT_PRESENT, /* "pattern present" signal */
977 AMPLC_DIO_GAT_PAT_OCCURRED, /* "pattern occurred" latched */
978 AMPLC_DIO_GAT_PAT_GONE, /* "pattern gone away" latched */
979 AMPLC_DIO_GAT_NPAT_PRESENT, /* negated "pattern present" */
980 AMPLC_DIO_GAT_NPAT_OCCURRED, /* negated "pattern occurred" */
981 AMPLC_DIO_GAT_NPAT_GONE /* negated "pattern gone away" */
982 };
983
984 #endif /* _COMEDI_H */
985