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Searched refs:HAS_PCH_SPLIT (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/i915/
Di915_ums.c43 if (HAS_PCH_SPLIT(dev)) in i915_pipe_enabled()
61 if (HAS_PCH_SPLIT(dev)) in i915_save_palette()
83 if (HAS_PCH_SPLIT(dev)) in i915_restore_palette()
110 if (HAS_PCH_SPLIT(dev)) { in i915_save_display_reg()
118 if (HAS_PCH_SPLIT(dev)) { in i915_save_display_reg()
127 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) in i915_save_display_reg()
135 if (!HAS_PCH_SPLIT(dev)) in i915_save_display_reg()
138 if (HAS_PCH_SPLIT(dev)) { in i915_save_display_reg()
175 if (HAS_PCH_SPLIT(dev)) { in i915_save_display_reg()
184 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) in i915_save_display_reg()
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Dintel_panel.c140 if (HAS_PCH_SPLIT(dev_priv->dev)) { in i915_read_blc_pwm_ctl()
173 if (HAS_PCH_SPLIT(dev)) { in _intel_panel_get_max_backlight()
231 if (HAS_PCH_SPLIT(dev)) { in intel_panel_get_backlight()
266 if (HAS_PCH_SPLIT(dev)) in intel_panel_actually_set_backlight()
307 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; in intel_panel_disable_backlight()
311 if (HAS_PCH_SPLIT(dev)) { in intel_panel_disable_backlight()
334 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; in intel_panel_enable_backlight()
357 if (HAS_PCH_SPLIT(dev)) { in intel_panel_enable_backlight()
Di915_suspend.c206 if (HAS_PCH_SPLIT(dev)) { in i915_save_display()
225 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) in i915_save_display()
228 if (HAS_PCH_SPLIT(dev)) { in i915_save_display()
240 if (HAS_PCH_SPLIT(dev)) { in i915_save_display()
269 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) in i915_restore_display()
280 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) in i915_restore_display()
283 if (HAS_PCH_SPLIT(dev)) { in i915_restore_display()
310 if (HAS_PCH_SPLIT(dev)) { in i915_restore_display()
341 if (HAS_PCH_SPLIT(dev)) { in i915_save_state()
392 if (HAS_PCH_SPLIT(dev)) { in i915_restore_state()
Dintel_lvds.c159 if (HAS_PCH_SPLIT(dev) || !enc->pfit_control) in intel_pre_enable_lvds()
187 if (HAS_PCH_SPLIT(dev)) { in intel_enable_lvds()
212 if (HAS_PCH_SPLIT(dev)) { in intel_disable_lvds()
345 if (HAS_PCH_SPLIT(dev)) { in intel_lvds_compute_config()
1089 if (HAS_PCH_SPLIT(dev)) { in intel_lvds_init()
1110 if (!HAS_PCH_SPLIT(dev)) { in intel_lvds_init()
1136 if (HAS_PCH_SPLIT(dev)) in intel_lvds_init()
1149 if (HAS_PCH_SPLIT(dev)) { in intel_lvds_init()
1233 if (HAS_PCH_SPLIT(dev)) in intel_lvds_init()
1263 if (HAS_PCH_SPLIT(dev)) { in intel_lvds_init()
Dintel_crt.c207 if (HAS_PCH_SPLIT(dev)) in intel_crt_compute_config()
226 if (HAS_PCH_SPLIT(dev)) in intel_crt_mode_set()
246 if (!HAS_PCH_SPLIT(dev)) in intel_crt_mode_set()
262 bool turn_off_dac = HAS_PCH_SPLIT(dev); in intel_ironlake_crt_detect_hotplug()
350 if (HAS_PCH_SPLIT(dev)) in intel_crt_detect_hotplug()
663 if (HAS_PCH_SPLIT(dev)) { in intel_crt_reset()
767 if (HAS_PCH_SPLIT(dev)) in intel_crt_init()
Dintel_hdmi.c605 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) in intel_hdmi_mode_set()
683 if (HAS_PCH_SPLIT(dev)) { in intel_enable_hdmi()
696 if (HAS_PCH_SPLIT(dev)) { in intel_enable_hdmi()
739 if (HAS_PCH_SPLIT(dev)) { in intel_disable_hdmi()
752 if (HAS_PCH_SPLIT(dev)) { in intel_disable_hdmi()
791 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) in intel_hdmi_compute_config()
799 if (pipe_config->pipe_bpp > 8*3 && HAS_PCH_SPLIT(dev)) { in intel_hdmi_compute_config()
1035 } else if (!HAS_PCH_SPLIT(dev)) { in intel_hdmi_init_connector()
Dintel_dp.c359 } else if (HAS_PCH_SPLIT(dev)) { in intel_dp_aux_ch()
680 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp)) in intel_dp_compute_config()
877 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) in intel_dp_mode_set()
2345 if (HAS_PCH_SPLIT(dev)) in intel_dp_detect()
2633 if (HAS_PCH_SPLIT(dev)) { in intel_dp_init_panel_power_sequencer()
2728 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); in intel_dp_init_panel_power_sequencer_registers()
2731 if (HAS_PCH_SPLIT(dev)) { in intel_dp_init_panel_power_sequencer_registers()
2795 if (HAS_PCH_SPLIT(dev) && port == PORT_D) in intel_dp_init_connector()
Di915_gem_stolen.c107 if (HAS_PCH_SPLIT(dev)) in i915_setup_compression()
Dintel_display.c102 WARN_ON(!HAS_PCH_SPLIT(dev)); in intel_pch_rawclk()
537 if (HAS_PCH_SPLIT(dev)) in intel_limit()
717 if (HAS_PCH_SPLIT(dev)) in intel_g4x_find_best_PLL()
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) { in assert_panel_unlocked()
1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) { in assert_planes_disabled()
1848 if (!HAS_PCH_SPLIT(dev_priv->dev)) in intel_enable_pipe()
3986 if (HAS_PCH_SPLIT(dev)) { in intel_crtc_compute_config()
6199 if (HAS_PCH_SPLIT(dev)) in intel_crtc_load_lut()
6875 if (HAS_PCH_SPLIT(dev)) in intel_increase_pllclock()
6903 if (HAS_PCH_SPLIT(dev)) in intel_decrease_pllclock()
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Dintel_i2c.c528 else if (HAS_PCH_SPLIT(dev)) in intel_setup_gmbus()
Dintel_bios.c763 if (!HAS_PCH_SPLIT(dev) && in intel_setup_bios()
Di915_irq.c158 if (HAS_PCH_SPLIT(dev)) in intel_enable_asle()
1511 if (HAS_PCH_SPLIT(dev)) in i915_capture_error_state()
1530 if (!HAS_PCH_SPLIT(dev)) in i915_capture_error_state()
3124 } else if (HAS_PCH_SPLIT(dev)) { in intel_irq_init()
Di915_drv.h1391 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) macro
1935 if (HAS_PCH_SPLIT(dev)) in i915_vgacntrl_reg()
Di915_debugfs.c470 } else if (!HAS_PCH_SPLIT(dev)) { in i915_interrupt_info()
1300 if (HAS_PCH_SPLIT(dev)) in i915_sr_status()
Dintel_sdvo.c1054 if (HAS_PCH_SPLIT(encoder->base.dev)) in intel_sdvo_compute_config()
1189 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi) in intel_sdvo_mode_set()
Dintel_pm.c4191 if (HAS_PCH_SPLIT(dev)) { in intel_init_pm()
4214 if (HAS_PCH_SPLIT(dev)) { in intel_init_pm()