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Searched refs:I915_WRITE (Results 1 – 25 of 30) sorted by relevance

12

/drivers/gpu/drm/i915/
Di915_ums.c92 I915_WRITE(reg + (i << 2), array[i]); in i915_restore_palette()
285 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->regfile.savePIPEA_GMCH_DATA_M); in i915_restore_display_reg()
286 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->regfile.savePIPEB_GMCH_DATA_M); in i915_restore_display_reg()
287 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->regfile.savePIPEA_GMCH_DATA_N); in i915_restore_display_reg()
288 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->regfile.savePIPEB_GMCH_DATA_N); in i915_restore_display_reg()
289 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->regfile.savePIPEA_DP_LINK_M); in i915_restore_display_reg()
290 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->regfile.savePIPEB_DP_LINK_M); in i915_restore_display_reg()
291 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->regfile.savePIPEA_DP_LINK_N); in i915_restore_display_reg()
292 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->regfile.savePIPEB_DP_LINK_N); in i915_restore_display_reg()
311 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]); in i915_restore_display_reg()
[all …]
Dintel_pm.c66 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_disable_fbc()
99 I915_WRITE(FBC_TAG + (i * 4), 0); in i8xx_enable_fbc()
104 I915_WRITE(FBC_CONTROL2, fbc_ctl2); in i8xx_enable_fbc()
105 I915_WRITE(FBC_FENCE_OFF, crtc->y); in i8xx_enable_fbc()
114 I915_WRITE(FBC_CONTROL, fbc_ctl); in i8xx_enable_fbc()
141 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); in g4x_enable_fbc()
143 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | in g4x_enable_fbc()
146 I915_WRITE(DPFC_FENCE_YOFF, crtc->y); in g4x_enable_fbc()
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); in g4x_enable_fbc()
163 I915_WRITE(DPFC_CONTROL, dpfc_ctl); in g4x_disable_fbc()
[all …]
Di915_suspend.c137 I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL); in i915_restore_vga()
139 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0); in i915_restore_vga()
140 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1); in i915_restore_vga()
141 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD); in i915_restore_vga()
263 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); in i915_restore_display()
270 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2); in i915_restore_display()
276 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask); in i915_restore_display()
278 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); in i915_restore_display()
281 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL); in i915_restore_display()
284 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL); in i915_restore_display()
[all …]
Di915_irq.c100 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_enable_display_irq()
110 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_disable_display_irq()
126 I915_WRITE(reg, pipestat); in i915_enable_pipestat()
140 I915_WRITE(reg, pipestat); in i915_disable_pipestat()
467 I915_WRITE(GEN6_PMIMR, 0); in gen6_pm_rps_work()
517 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in ivybridge_parity_work()
525 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID | in ivybridge_parity_work()
529 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in ivybridge_parity_work()
533 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in ivybridge_parity_work()
565 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in ivybridge_handle_parity_error()
[all …]
Dintel_sprite.c118 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); in vlv_update_plane()
119 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); in vlv_update_plane()
129 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); in vlv_update_plane()
131 I915_WRITE(SPLINOFF(pipe, plane), linear_offset); in vlv_update_plane()
133 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); in vlv_update_plane()
134 I915_WRITE(SPCNTR(pipe, plane), sprctl); in vlv_update_plane()
149 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) & in vlv_disable_plane()
170 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); in vlv_update_colorkey()
171 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); in vlv_update_colorkey()
172 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); in vlv_update_colorkey()
[all …]
Dintel_hdmi.c153 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
157 I915_WRITE(VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
162 I915_WRITE(VIDEO_DIP_DATA, 0); in g4x_write_infoframe()
169 I915_WRITE(VIDEO_DIP_CTL, val); in g4x_write_infoframe()
191 I915_WRITE(reg, val); in ibx_write_infoframe()
195 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in ibx_write_infoframe()
200 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in ibx_write_infoframe()
207 I915_WRITE(reg, val); in ibx_write_infoframe()
232 I915_WRITE(reg, val); in cpt_write_infoframe()
236 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in cpt_write_infoframe()
[all …]
Dintel_ddi.c106 I915_WRITE(reg, ddi_translations[i]); in intel_prepare_ddi_buffers()
178 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | in hsw_fdi_link_train()
185 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); in hsw_fdi_link_train()
191 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); in hsw_fdi_link_train()
194 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel); in hsw_fdi_link_train()
200 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
210 I915_WRITE(DDI_BUF_CTL(PORT_E), in hsw_fdi_link_train()
219 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); in hsw_fdi_link_train()
223 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); in hsw_fdi_link_train()
232 I915_WRITE(_FDI_RXA_MISC, temp); in hsw_fdi_link_train()
[all …]
Dintel_tv.c859 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
868 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
1050 I915_WRITE(TV_H_CTL_1, hctl1); in intel_tv_mode_set()
1051 I915_WRITE(TV_H_CTL_2, hctl2); in intel_tv_mode_set()
1052 I915_WRITE(TV_H_CTL_3, hctl3); in intel_tv_mode_set()
1053 I915_WRITE(TV_V_CTL_1, vctl1); in intel_tv_mode_set()
1054 I915_WRITE(TV_V_CTL_2, vctl2); in intel_tv_mode_set()
1055 I915_WRITE(TV_V_CTL_3, vctl3); in intel_tv_mode_set()
1056 I915_WRITE(TV_V_CTL_4, vctl4); in intel_tv_mode_set()
1057 I915_WRITE(TV_V_CTL_5, vctl5); in intel_tv_mode_set()
[all …]
Dintel_i2c.c65 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); in intel_i2c_reset()
66 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); in intel_i2c_reset()
82 I915_WRITE(DSPCLK_GATE_D, val); in intel_i2c_quirk_set()
229 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); in gmbus_wait_hw_status()
243 I915_WRITE(GMBUS4 + reg_offset, 0); in gmbus_wait_hw_status()
264 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); in gmbus_wait_idle()
269 I915_WRITE(GMBUS4 + reg_offset, 0); in gmbus_wait_idle()
286 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_read()
325 I915_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer_write()
326 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_write()
[all …]
Dintel_display.c442 I915_WRITE(DPIO_REG, reg); in intel_dpio_read()
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | in intel_dpio_read()
463 I915_WRITE(DPIO_DATA, val); in intel_dpio_write()
464 I915_WRITE(DPIO_REG, reg); in intel_dpio_write()
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | in intel_dpio_write()
476 I915_WRITE(DPIO_CTL, 0); in vlv_init_dpio()
478 I915_WRITE(DPIO_CTL, 1); in vlv_init_dpio()
940 I915_WRITE(pipestat_reg, in intel_wait_for_vblank()
1489 I915_WRITE(reg, val); in intel_enable_pll()
1492 I915_WRITE(reg, val); in intel_enable_pll()
[all …]
Dintel_crt.c115 I915_WRITE(crt->adpa_reg, temp); in intel_crt_set_dpms()
247 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0); in intel_crt_mode_set()
249 I915_WRITE(crt->adpa_reg, adpa); in intel_crt_mode_set()
274 I915_WRITE(crt->adpa_reg, adpa); in intel_ironlake_crt_detect_hotplug()
281 I915_WRITE(crt->adpa_reg, save_adpa); in intel_ironlake_crt_detect_hotplug()
311 I915_WRITE(crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
316 I915_WRITE(crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
370 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); in intel_crt_detect_hotplug()
383 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); in intel_crt_detect_hotplug()
386 I915_WRITE(PORT_HOTPLUG_EN, orig); in intel_crt_detect_hotplug()
[all …]
Dintel_panel.c146 I915_WRITE(BLC_PWM_PCH_CTL2, val); in i915_read_blc_pwm_ctl()
157 I915_WRITE(BLC_PWM_CTL, val); in i915_read_blc_pwm_ctl()
159 I915_WRITE(BLC_PWM_CTL2, in i915_read_blc_pwm_ctl()
255 I915_WRITE(BLC_PWM_CPU_CTL, val | level); in intel_pch_panel_set_backlight()
282 I915_WRITE(BLC_PWM_CTL, tmp | level); in intel_panel_actually_set_backlight()
309 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE); in intel_panel_disable_backlight()
314 I915_WRITE(BLC_PWM_PCH_CTL1, tmp); in intel_panel_disable_backlight()
353 I915_WRITE(reg, tmp); in intel_panel_enable_backlight()
355 I915_WRITE(reg, tmp | BLM_PWM_ENABLE); in intel_panel_enable_backlight()
361 I915_WRITE(BLC_PWM_PCH_CTL1, tmp); in intel_panel_enable_backlight()
Ddvo_ns2501.c106 I915_WRITE(DVOC, 0x10004084); in enable_dvo()
107 I915_WRITE(_DPLL_A, 0xd0820000); in enable_dvo()
108 I915_WRITE(DVOC_SRCDIM, 0x400300); // 1024x768 in enable_dvo()
109 I915_WRITE(FW_BLC, 0x1080304); in enable_dvo()
111 I915_WRITE(DVOC, 0x90004084); in enable_dvo()
127 I915_WRITE(DVOC, ns->dvoc); in restore_dvo()
128 I915_WRITE(_DPLL_A, ns->pll_a); in restore_dvo()
129 I915_WRITE(DVOC_SRCDIM, ns->srcdim); in restore_dvo()
130 I915_WRITE(FW_BLC, ns->fw_blc); in restore_dvo()
Dintel_ringbuffer.h22 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
25 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
28 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
31 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
34 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
Di915_gem_gtt.c109 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | in gen6_ppgtt_enable()
113 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); in gen6_ppgtt_enable()
116 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | in gen6_ppgtt_enable()
118 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
123 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); in gen6_ppgtt_enable()
132 I915_WRITE(GAM_ECOCHK, ecochk); in gen6_ppgtt_enable()
138 I915_WRITE(RING_MODE_GEN7(ring), in gen6_ppgtt_enable()
141 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); in gen6_ppgtt_enable()
142 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); in gen6_ppgtt_enable()
458 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); in gen6_ggtt_insert_entries()
Dintel_dp.c389 I915_WRITE(ch_data + i, in intel_dp_aux_ch()
393 I915_WRITE(ch_ctl, in intel_dp_aux_ch()
407 I915_WRITE(ch_ctl, in intel_dp_aux_ch()
796 I915_WRITE(DP_A, dpa_ctl); in ironlake_set_pll_edp()
1007 I915_WRITE(pp_ctrl_reg, pp); in ironlake_edp_panel_vdd_on()
1036 I915_WRITE(pp_ctrl_reg, pp); in ironlake_panel_vdd_off_sync()
1103 I915_WRITE(PCH_PP_CONTROL, pp); in ironlake_edp_panel_on()
1113 I915_WRITE(pp_ctrl_reg, pp); in ironlake_edp_panel_on()
1120 I915_WRITE(PCH_PP_CONTROL, pp); in ironlake_edp_panel_on()
1146 I915_WRITE(pp_ctrl_reg, pp); in ironlake_edp_panel_off()
[all …]
Dintel_ringbuffer.c513 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); in init_render_ring()
520 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in init_render_ring()
524 I915_WRITE(GFX_MODE, in init_render_ring()
528 I915_WRITE(GFX_MODE_GEN7, in init_render_ring()
544 I915_WRITE(CACHE_MODE_0, in init_render_ring()
556 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in init_render_ring()
784 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in gen5_ring_get_irq()
802 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in gen5_ring_put_irq()
821 I915_WRITE(IMR, dev_priv->irq_mask); in i9xx_ring_get_irq()
839 I915_WRITE(IMR, dev_priv->irq_mask); in i9xx_ring_put_irq()
[all …]
Dintel_lvds.c150 I915_WRITE(lvds_encoder->reg, temp); in intel_pre_pll_enable_lvds()
172 I915_WRITE(PFIT_PGM_RATIOS, enc->pfit_pgm_ratios); in intel_pre_enable_lvds()
173 I915_WRITE(PFIT_CONTROL, enc->pfit_control); in intel_pre_enable_lvds()
195 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
197 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_enable_lvds()
222 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_disable_lvds()
226 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); in intel_disable_lvds()
371 I915_WRITE(BCLRPAT(pipe), 0); in intel_lvds_compute_config()
1264 I915_WRITE(PCH_PP_CONTROL, in intel_lvds_init()
1267 I915_WRITE(PP_CONTROL, in intel_lvds_init()
Di915_gem_stolen.c108 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start); in i915_setup_compression()
110 I915_WRITE(DPFC_CB_BASE, compressed_fb->start); in i915_setup_compression()
122 I915_WRITE(FBC_CFB_BASE, in i915_setup_compression()
124 I915_WRITE(FBC_LL_BASE, in i915_setup_compression()
Dintel_dvo.c140 I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); in intel_disable_dvo()
151 I915_WRITE(dvo_reg, temp | DVO_ENABLE); in intel_enable_dvo()
287 I915_WRITE(dpll_reg, I915_READ(dpll_reg) | DPLL_DVO_HIGH_SPEED); in intel_dvo_mode_set()
292 I915_WRITE(dvo_srcdim_reg, in intel_dvo_mode_set()
296 I915_WRITE(dvo_reg, dvo_val); in intel_dvo_mode_set()
Di915_drv.c742 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); in i8xx_do_reset()
746 I915_WRITE(DEBUG_RESET_I830, in i8xx_do_reset()
753 I915_WRITE(DEBUG_RESET_I830, 0); in i8xx_do_reset()
759 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); in i8xx_do_reset()
807 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, in ironlake_do_reset()
816 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, in ironlake_do_reset()
Dintel_overlay.c1298 I915_WRITE(OGAMC0, attrs->gamma0); in intel_overlay_attrs()
1299 I915_WRITE(OGAMC1, attrs->gamma1); in intel_overlay_attrs()
1300 I915_WRITE(OGAMC2, attrs->gamma2); in intel_overlay_attrs()
1301 I915_WRITE(OGAMC3, attrs->gamma3); in intel_overlay_attrs()
1302 I915_WRITE(OGAMC4, attrs->gamma4); in intel_overlay_attrs()
1303 I915_WRITE(OGAMC5, attrs->gamma5); in intel_overlay_attrs()
Di915_gem.c2604 I915_WRITE(reg, val); in i915_write_fence_reg()
2636 I915_WRITE(FENCE_REG_830_0 + reg * 4, val); in i830_write_fence_reg()
3897 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in i915_gem_l3_remap()
3907 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); in i915_gem_l3_remap()
3913 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in i915_gem_l3_remap()
3924 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in i915_gem_init_swizzling()
3930 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); in i915_gem_init_swizzling()
3932 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in i915_gem_init_swizzling()
3934 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in i915_gem_init_swizzling()
4002 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); in i915_gem_init_hw()
[all …]
Di915_sysfs.c133 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in i915_l3_read()
138 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in i915_l3_read()
Dintel_bios.c766 I915_WRITE(PP_ON_DELAYS, 0x019007d0); in intel_setup_bios()
769 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0); in intel_setup_bios()

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