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Searched refs:I915_WRITE16 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/
Di915_irq.c407 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); in ironlake_handle_rps_change()
411 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); in ironlake_handle_rps_change()
2427 I915_WRITE16(IMR, 0xffff); in i8xx_irq_preinstall()
2428 I915_WRITE16(IER, 0x0); in i8xx_irq_preinstall()
2436 I915_WRITE16(EMR, in i8xx_irq_postinstall()
2446 I915_WRITE16(IMR, dev_priv->irq_mask); in i8xx_irq_postinstall()
2448 I915_WRITE16(IER, in i8xx_irq_postinstall()
2535 I915_WRITE16(IIR, iir & ~flip_mask); in i8xx_irq_handler()
2567 I915_WRITE16(IMR, 0xffff); in i8xx_irq_uninstall()
2568 I915_WRITE16(IER, 0x0); in i8xx_irq_uninstall()
[all …]
Dintel_pm.c2319 I915_WRITE16(MEMSWCTL, rgvswctl); in ironlake_set_drps()
2323 I915_WRITE16(MEMSWCTL, rgvswctl); in ironlake_set_drps()
2337 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); in ironlake_enable_drps()
2338 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); in ironlake_enable_drps()
4061 I915_WRITE16(DEUC, 0); in crestline_init_clock_gating()
Dintel_ringbuffer.c858 I915_WRITE16(IMR, dev_priv->irq_mask); in i8xx_ring_get_irq()
876 I915_WRITE16(IMR, dev_priv->irq_mask); in i8xx_ring_put_irq()
Di915_drv.h1913 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) macro