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Searched refs:IOAT_CHANERR_OFFSET (Results 1 – 6 of 6) sorted by relevance

/drivers/dma/ioat/
Ddma_v2.c313 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat2_timer_event()
358 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat2_reset_hw()
359 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); in ioat2_reset_hw()
572 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat2_alloc_chan_resources()
Ddma.c205 chanerr = readl(reg_base + IOAT_CHANERR_OFFSET); in ioat1_reset_channel()
211 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET); in ioat1_reset_channel()
326 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat1_dma_alloc_chan_resources()
329 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); in ioat1_dma_alloc_chan_resources()
561 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat_get_current_completion()
Dregisters.h228 #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ macro
Ddma_v3.c637 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_cleanup()
683 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_eh()
720 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_eh()
772 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_timer_event()
1798 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_reset_hw()
1799 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); in ioat3_reset_hw()
Ddma.h283 return readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat_chanerr()
/drivers/idle/
Di7300_idle.c109 err = readl(ioat_chanbase + IOAT_CHANERR_OFFSET); in i7300_idle_ioat_start()
111 writel(err, ioat_chanbase + IOAT_CHANERR_OFFSET); in i7300_idle_ioat_start()