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Searched refs:IS_VALLEYVIEW (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_dp.c226 if (IS_VALLEYVIEW(dev)) in intel_hrawclk()
258 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; in ironlake_edp_have_panel_power()
268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_edp_have_panel_vdd()
282 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; in intel_dp_check_edp()
283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in intel_dp_check_edp()
331 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); in intel_dp_aux_ch()
350 else if (IS_VALLEYVIEW(dev)) in intel_dp_aux_ch()
859 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { in intel_dp_mode_set()
877 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) in intel_dp_mode_set()
892 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { in intel_dp_mode_set()
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Dintel_crt.c353 if (IS_VALLEYVIEW(dev)) in intel_crt_detect_hotplug()
769 else if (IS_VALLEYVIEW(dev)) in intel_crt_init()
Di915_gem_tiling.c94 if (IS_VALLEYVIEW(dev)) { in i915_gem_detect_bit_6_swizzle()
Dintel_sprite.c921 if (IS_HASWELL(dev) || IS_VALLEYVIEW(dev)) in intel_plane_init()
926 if (IS_VALLEYVIEW(dev)) { in intel_plane_init()
Di915_drv.h1323 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) macro
1348 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1937 else if (IS_VALLEYVIEW(dev)) in i915_vgacntrl_reg()
Dintel_hdmi.c605 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) in intel_hdmi_mode_set()
1032 if (IS_VALLEYVIEW(dev)) { in intel_hdmi_init_connector()
Dintel_display.c546 } else if (IS_VALLEYVIEW(dev)) { in intel_limit()
1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) { in assert_planes_disabled()
1297 if (!IS_VALLEYVIEW(dev_priv->dev)) in assert_sprites_disabled()
1478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); in intel_enable_pll()
4006 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { in intel_crtc_compute_config()
4155 if (IS_VALLEYVIEW(dev)) { in i9xx_get_refclk()
4590 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base, in i9xx_set_pipeconf()
4616 if (IS_VALLEYVIEW(dev)) { in i9xx_set_pipeconf()
4714 else if (IS_VALLEYVIEW(dev)) in i9xx_crtc_mode_set()
4724 if (!IS_VALLEYVIEW(dev)) { in i9xx_crtc_mode_set()
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Dintel_i2c.c530 else if (IS_VALLEYVIEW(dev)) in intel_setup_gmbus()
Dintel_pm.c3471 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { in intel_disable_gt_powersave()
3500 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { in intel_enable_gt_powersave()
4257 } else if (IS_VALLEYVIEW(dev)) { in intel_init_pm()
4493 if (IS_VALLEYVIEW(dev)) { in intel_gt_reset()
4510 if (IS_VALLEYVIEW(dev)) { in intel_gt_init()
Di915_irq.c153 if (IS_VALLEYVIEW(dev)) in intel_enable_asle()
1513 else if (IS_VALLEYVIEW(dev)) in i915_capture_error_state()
1523 if (IS_VALLEYVIEW(dev)) in i915_capture_error_state()
3107 if (IS_VALLEYVIEW(dev)) { in intel_irq_init()
Di915_debugfs.c432 if (IS_VALLEYVIEW(dev)) { in i915_interrupt_info()
1633 if (!IS_VALLEYVIEW(dev)) { in i915_dpio_info()
Di915_dma.c1638 if (IS_VALLEYVIEW(dev)) in i915_driver_load()
Di915_gem.c4041 if (IS_VALLEYVIEW(dev)) { in i915_gem_init()
4184 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) in i915_gem_load()