Searched refs:MC (Results 1 – 15 of 15) sorted by relevance
| /drivers/memory/ |
| D | Kconfig | 24 bool "Tegra20 Memory Controller(MC) driver"
28 This driver is for the Memory Controller(MC) module available
34 bool "Tegra30 Memory Controller(MC) driver"
38 This driver is for the Memory Controller(MC) module available
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| /drivers/char/ |
| D | hpet.c | 62 #define write_counter(V, MC) writeq(V, MC) argument
63 #define read_counter(MC) readq(MC) argument
65 #define write_counter(V, MC) writel(V, MC) argument
66 #define read_counter(MC) readl(MC) argument
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| /drivers/misc/ |
| D | bmp085.c | 72 s16 MB, MC, MD; member
108 cali->MC = be16_to_cpu(tmp[9]); in bmp085_read_calibration_data()
194 x2 = (cali->MC << 11) / (x1 + cali->MD); in bmp085_get_temperature()
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| /drivers/gpu/drm/nouveau/core/subdev/mc/ |
| D | nv98.c | 68 .handle = NV_SUBDEV(MC, 0x98),
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| D | nvc0.c | 70 .handle = NV_SUBDEV(MC, 0xc0),
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| D | nv44.c | 66 .handle = NV_SUBDEV(MC, 0x44),
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| D | nv50.c | 74 .handle = NV_SUBDEV(MC, 0x50),
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| D | nv04.c | 75 .handle = NV_SUBDEV(MC, 0x04),
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| /drivers/staging/media/davinci_vpfe/ |
| D | TODO | 7 - Use of MC and V4L2 subdev APIs when applicable
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| /drivers/scsi/csiostor/ |
| D | csio_hw.h | 121 #define CSIO_GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
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| D | csio_hw.c | 3274 if (cause & MC) in csio_hw_slow_intr_handler()
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| /drivers/media/dvb-frontends/ |
| D | Kconfig | 356 tristate "DiBcom 7000MA/MB/PA/PB/MC"
592 tristate "DiBcom 8000MB/MC"
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| /drivers/edac/ |
| D | Kconfig | 248 tristate "Intel Sandy-Bridge Integrated MC"
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| /drivers/net/ethernet/chelsio/cxgb4/ |
| D | t4_regs.h | 1066 #define MC 0x00008000U macro
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| D | t4_hw.c | 1813 #define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
1851 if (cause & MC) in t4_slow_intr_handler()
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